at94k10al ATMEL Corporation, at94k10al Datasheet - Page 142

• Manufacturer Part Number: at94k10al
• Description: At94k05al 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

142
AT94KAL Series FPSLIC
• Bits 7..0 - 2-wire Serial Bit-rate Register
TWBR selects the division factor for the bit-rate generator. The bit-rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes according to the following
equation:
Both the receiver and the transmitter can stretch the Low period of the SCL line when waiting for
user response, thereby reducing the average bit rate.
The 2-wire Serial Control Register – TWCR
• Bit 7 - TWINT: 2-wire Serial Interrupt Flag
This bit is set by the hardware when the 2-wire Serial Interface has finished its current job and
expects application software response. If the I-bit in the SREG and TWIE in the TWCR register
are set (one), the MCU will jump to the interrupt vector at address $0046. While the TWINT flag
is set, the bus SCL clock line Low period is stretched. The TWINT flag must be cleared by soft-
ware by writing a logic 1 to it. Note that this flag is not automatically cleared by the hardware
when executing the interrupt routine. Also note that clearing this flag starts the operation of the
2-wire Serial Interface, so all accesses to the 2-wire Serial Address Register – TWAR, 2-wire
Serial Status Register – TWSR, and 2-wire Serial Data Register – TWDR must be complete
before clearing this flag.
• Bit 6 - TWEA: 2-wire Serial Enable Acknowledge Flag
TWEA flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the ACK
pulse is generated on the 2-wire Serial Bus if the following conditions are met:
By setting the TWEA bit Low the device can be virtually disconnected from the 2-wire Serial Bus
temporarily. Address recognition can then be resumed by setting the TWEA bit again.
• Bit 5 - TWSTA: 2-wire Serial Bus START Condition Flag
The TWSTA flag is set by the CPU when it desires to become a Master on the 2-wire Serial Bus.
The 2-wire serial hardware checks if the bus is available, and generates a Start condition on the
bus if the bus is free. However, if the bus is not free, the 2-wire Serial Interface waits until a
STOP condition is detected, and then generates a new Start condition to claim the bus Master
status.
Bit
$36 ($56)
Read/Write
Initial Value
• Bit-rate = SCL frequency
• f
• TWBR = Contents of the 2-wire Serial Bit Rate Register
• The device’s own Slave address has been detected
• A general call has been received, while the TWGCE bit in the TWAR is set
• A data byte has been received in Master Receiver or Slave Receiver mode
CK
= CPU Clock frequency
Bit-rate
7
TWINT
R/W
0
=
6
TWEA
R/W
0
------------------------------------- -
16 + 2(TWBR)
f
CK
5
TWSTA
R/W
0
4
TWSTO
R/W
0
3
TWWC
R
0
2
TWEN
R/W
0
1
-
R
0
0
TWIE
R/W
0
1138I–FPSLI–1/08
TWCR