at94k10al ATMEL Corporation, at94k10al Datasheet - Page 88

• Manufacturer Part Number: at94k10al
• Description: At94k05al 5k - 40k Gates Of At40k Fpga With 8-bit Microcontroller, Up To 36k Bytes Of Sram And On-chip Jtag Ice
• Manufacturer: ATMEL Corporation

4.22.5
88
AT94KAL Series FPSLIC
Boundary-scan Description Language Files
Table 4-12.
Boundary-Scan Description Language (BSDL) files describe Boundary-Scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-Scan data register are included in this description. A BSDL file for AT94K Family
is available.
Enable Clock - TOSC 1
Enable Output - SDA
Enable Output - SCL
Clock Out/In - SCL
Data Out/In - SDA
Bit EXTEST and SAMPLE_PRELOAD (Continued)
AVR Reset
Bit Type
EXTEST
1 = clock disabled. Capture-DR
grabs clock enable from the AVR.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Observe only. Capture-DR grabs
signal from pad.
1 = drive “0”
0 = drive disabled, bus pull-up
Capture-DR grabs output enable
scan latch.
Internal, observe only.
Capture-DR grabs internal AVR
reset signal.
SAMPLE_PRELOAD
Capture-DR grabs enable from
the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs signal from
pad.
Capture-DR grabs output enable
from the AVR.
Capture-DR grabs internal AVR
reset signal.
1138I–FPSLI–1/08