cy8c26233-24sxit Cypress Semiconductor Corporation., cy8c26233-24sxit Datasheet - Page 52

• Manufacturer Part Number: cy8c26233-24sxit
• Description: 8-bit Programmable System-on-chip Psoc? Microcontrollers
• Manufacturer: Cypress Semiconductor Corporation.

Digital Communications Type A Block 06 Input Register
Digital Communications Type A Block 07 Input Register
The Data/Enable source select [3:0] bits select between
multiple inputs to the Digital PSoC Blocks. These inputs
serve as Clock Enables or Data Input depending on the
Digital PSoC Block’s programmed function. If “Chain
Function to Previous” data input is selected for Data/
Enable then the selected Digital PSoC block receives its
Data, Enable, Zero Detect, and all chaining information
from the previous digital PSoC block. The data inputs
that are selected from the GPIO pins (through the Global
Input Bus) are synchronized to the 24 MHz clock. The
following table shows the function dependent meaning of
the data input.
Table 49:
9.2.3
The digital PSoC block’s outputs can be selected to drive
associated Global Output Bus signals via the Output
Select bits. In addition, the output drive can be selec-
tively enabled in this register. The SPI Slave has an aux-
iliary input which is also controlled by selections in this
register.
52
Timer
Counter
CRC
PRS
Deadband
TX UART
RX UART
SPI Master
SPI Slave
Function
Digital Function Data Input Definitions
Digital Basic Type A / Communications Type A Block xx Output Register
Positive Edge Capture
Count Enable (Active High)
Data Input
N/A
Kill Signal (Active High)
N/A
RX Data In
MISO (Master In/Slave Out)
MOSI (Master Out/Slave In)
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Data Input
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
The Clock[3:0] bits select multiple sources for the clock
for each digital PSoC block. The sources for each digital
PSoC block clock are selected from the Global Input
Bus, System Clocks, and other neighboring digital PSoC
blocks. As shown in the table, Digital PSoC Blocks 0-3
can interface to Global I/Os 00-03, and Digital PSoC
block 04-07 can interface to Global I/Os 4-7. It is impor-
tant to note that clock inputs selected from the GPIO pins
(through the Global Input Bus) are not synchronized.
This may cause indeterminate results if the CPU reads a
block register as it is changing in response to an external
clock. CPU reads must be manually synchronized, either
through the block interrupt, or through a multiple read
and voting scheme.
(DCA06IN, Address = Bank 1, 39h)
(DCA07IN, Address = Bank 1, 3Dh)
September 5, 2002