ml675050 Oki Semiconductor, ml675050 Datasheet - Page 38

• Manufacturer Part Number: ml675050
• Description: Arm7tdmi Based Micro-controller For Ic Card Reader/writer
• Manufacturer: Oki Semiconductor

ROMCS_N, RAMCS_N Read
access time (ROM/SRAM)
ROMCS_N, RAMCS_N Write
access time (ROM/SRAM)
ROMCS_N, RAMCS_N
Page mode access time
(ROM/SRAM)
XA[23:0] Read access time
(ROM/SRAM)
XA[23:0] Write access time
(ROM/SRAM)
XA[23:0] Page mode access
time (ROM/SRAM)
BS0_N, BS1_N Read access
time (ROM/SRAM)
BS0_N, BS1_N Write access
time (ROM/SRAM)
BS0_N, BS1_N Page mode
access time (ROM/SRAM)
RD_N pulse width
(ROM/SRAM)
RD_N pulse width
(ROM/SRAM: Page mode)
WR_N pulse width
(ROM/SRAM)
ROMCS_N, RAMCS_N output
hold time (ROM/SRAM : Read)
ROMCS_N, RAMCS_N output
hold time (ROM/SRAM : Write)
XA[23:0] output hold time 1
(ROM/SRAM : Read)
XA[23:0] output hold time 2
(ROM/SRAM : Read)
XA[23:0] output hold time
(ROM/SRAM : Write)
BS0_N, BS1_N output hold
time 1 (ROM/SRAM : Read)
BS0_N, BS1_N output hold
time 2 (ROM/SRAM : Read)
BS0_N, BS1_N output hold
time (ROM/SRAM : Write)
XD[15:0] input setup time 1
(ROM/SRAM)
XD[15:0] input setup time 2
(ROM/SRAM)
XD[15:0] input hold time 1
(ROM/SRAM)
XD[15:0] input hold time 2
(ROM/SRAM)
XD[15:0] output setup time
(ROM/SRAM)
XD[15:0] output hold time
(ROM/SRAM)
ELECTRICAL CHARACTERISTICS (AC CHARACTERISTICS)
(11) External ROM, SRAM Timing (1/5)
OKI Semiconductor
Parameter
Symbol Condition
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CSRACC
CSWACC
CSPACC
XARACC
XAWACC
XAPACC
RDW
PRDW
WRW
CSRH
CSWH
XARH1
XARH2
XAWH
BSRH1
BSRH2
BSWH
XDIS1
XDIS2
XDIH1
XDIH2
XDOS
XDOH
BSWACC
BSRACC
BSPACC
30 pF
CL
=
(n
(n
(n
– 3
(n
(n
n
n
n
n
n
(n
n
t
t
3
t
t
3
t
t
15.5
15.5
0
0
n
t
HC
HC
HC
HC
HC
HC
HC
R4
R4
R4
R4
R2
R2
R2
R1
R1
R1
R1
R1
R2
t
t
t
t
t
t
t
HC
HC
HC
HC
HC
HC
– 3
– 3
– 3
– 3
– 3
– 3
– 6
+n
+n
+n
+n
+n
+3*n
HC
R2
R2
R2
R2
R2
– 6
– 6
– 6
– 6
- 4
– 4
– 6
Min.
) t
) t
+3*n
) t
) t
R4
HC
HC
HC
HC
) t
HC
– 3
– 3
R4
– 6
– 6
) t
– 4
HC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
—
—
(n
(n
(n
+ 3
(n
(n
n
n
n
n
n
(n
n
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R4
R4
R4
R4
R2
R2
R1
R1
R1
R1
R1
R2
t
t
t
t
t
t
HC
HC
HC
HC
HC
HC
+n
+n
+n
+n
+n
+3*n
Max.
R2
R2
R2
R2
R2
+ 6
+ 6
+ 6
+ 6
+ 4
+ 4
+3*n
) t
) t
) t
) t
R4
HC
HC
HC
HC
) t
HC
R4
+ 3
+ 3
+ 6
+ 6
) t
+ 4
HC
Unit
ns
The RD_N/WR_N
pulse width and the
read off time when
accessing
SRAM/ROM are the
parameters that can
be set by the ROMAC/
RAMAC register.
See Table below for
details.
n
n
n
n
t
HC
R1
R2
R3
R4
= AHB_CLK cycle
FEDL675050-02
= Address setup
= RD_N, WR_N
= Data off time
= Burst timing
pulse width
Remarks
ML675050
38/62