ml675050 Oki Semiconductor, ml675050 Datasheet - Page 43

• Manufacturer Part Number: ml675050
• Description: Arm7tdmi Based Micro-controller For Ic Card Reader/writer
• Manufacturer: Oki Semiconductor

ELECTRICAL CHARACTERISTICS (AC CHARACTERISTICS)
(12) ROMAC register and timing parameters that can be set
ROMTYPE
[2:0]
000
001
010
011
100
101
110
111
(13) RAMAC register and timing parameters that can be set
RAMTYPE
[2:0]
000
001
010
011
100
101
110
111
OKI Semiconductor
(Please see ML675050 User’s manual when refer to the ROMAC register in detail)
The following timing parameters can be set:
The timing that can be set depends on memory to be connected. It is necessary to perform optimum setting
according to the bus speed.
ROMTYPE[2:0]: Setting of Timing Parameters (values in the table indicate AHB_CLK count)
(Please see ML675050 User’s manual when refer to the RAMAC register in detail)
The following timing parameters can be set:
RAMTYPE[2:0]: Setting of Timing Parameters (Values in the table indicate AHB_CLK count)
-
-
-
-
-
-
-
-
*1: Data off timing will be three cycles when accessing from the DMAC.
Address setup
RD_N, WR_N pulse width
Data off timing (period for waiting the ROM output floating delay time from RD_N deassert)
Burst timing (period from confirming the address in the page to sampling valid data)
Address setup
RD_N, WR_N pulse width
Data off timing (period for waiting the SRAM output floating delay time from RD_N deassert)
Burst timing (period from confirming the address in the page to sampling valid data)
For ROMAC, see Section 8.4.2, “ROM Access Control Register.”
For RAMAC, see Section 8.4.3, “SRAM Access Control Register.”
Address setup
Address setup
1
1
1
1
2
2
2
2
1
1
1
1
2
2
2
2
RD_N/WR_N
pulse width
1
2
3
5
8
10
13
16
RD_N/WR_N
pulse width
1
2
3
5
8
10
13
16
Data off timing
Data off timing
1
2
3
3
4
5
6
7
1
2
3
3
4
5
6
7
(*1)
Burst timing
1
2
3
3
5
6
7
9
Burst timing
1
2
3
3
5
6
7
9
Remarks
Setting when using a
high-speed ROM
Setting when using a
low-speed ROM
Remarks
Setting when using a
high-speed SRAM
Setting when using a
low-speed SRAM
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