at43usb355 ATMEL Corporation, at43usb355 Datasheet - Page 48

• Manufacturer Part Number: at43usb355
• Description: At43usb355 Full-speed Usb Microcontroller With Embedded Hub, Adc And Pwm
• Manufacturer: ATMEL Corporation

48
AT43USB355
Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL
Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared
with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con-
trol and Status register.A compare match does only occur if Timer/Counter1 counts to the
OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does
not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the com-
pare event.
Since the Output Compare Registers OCR1A and OCR1B are 16-bit registers, a temporary
register TEMP is used when OCR1A/B are written to ensure that both bytes are updated
simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo-
rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL,
the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high
byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and
also interrupt routines perform access to registers using TEMP, interrupts must be disabled
during access from the main program and from interrupt routines if interrupts are allowed from
within interrupt routines.
Read/Write
Initial Value
Initial Value
Read/Write
$2B ($4B)
$2A ($4A)
$29 ($49)
$28 ($48)
Bit
Bit
MSB
MSB
R/W
R/W
R/W
R/W
15
15
–
7
0
0
–
7
0
0
R/W
R/W
R/W
R/W
14
14
–
–
6
0
0
–
–
6
0
0
R/W
R/W
R/W
R/W
13
13
–
–
5
0
0
–
–
5
0
0
R/W
R/W
R/W
R/W
12
12
–
–
4
0
0
–
–
4
0
0
R/W
R/W
R/W
R/W
11
11
–
–
3
0
0
–
–
3
0
0
R/W
R/W
R/W
R/W
10
10
–
–
2
0
0
–
–
2
0
0
R/W
R/W
R/W
R/W
9
–
–
1
0
0
9
–
–
1
0
0
LSB
R/W
R/W
LSB
R/W
R/W
8
–
0
0
0
8
–
0
0
0
2603G–USB–04/06
OCR1AH
OCR1AL
OCR1BH
OCR1BL