z85c30 ZiLOG Semiconductor, z85c30 Datasheet - Page 13

• Manufacturer Part Number: z85c30
• Description: Cmos Scc Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

PS011705-0608
Z85C30
Z80C30
A/B
Channel A/Channel B (input) —
Write operation occurs.
CE
Chip Enable (input, active Low) —
operation.
D7–D0
Data Bus (bidirectional, tri-state) —
the SCC.
D/C
Data/Control Select (input) —
or from the SCC. A High indicates a data transfer; a Low indicates a command.
RD
Read (input, active Low) —
selected, enables the SCC’s bus drivers. During the Interrupt Acknowledge cycle, this
signal gates the interrupt vector onto the bus if the SCC is the highest priority device
requesting an interrupt.
WR
Write (input, active Low) —
operation. The coincidence of RD and WR is interpreted as a reset.
AD7–AD0
Address/Data Bus (bidirectional, active High, Tri-state) —
carry register addresses to the SCC as well as data or control information.
AS
Address Strobe (input, active Low) —
rising edge of this signal.
CS0
Chip Select 0 (input, active Low) —
addresses on AD7–AD0 and must be active for the intended bus transaction to occur.
This signal indicates a Read operation and when the SCC is
When the SCC is selected, this signal indicates a Write
This signal defines the type of information transferred to
This signal selects the channel in which the Read or
CMOS SCC Serial Communications Controller
This signal selects the SCC for a Read or Write
This signal is latched concurrently with the
These lines carry data and command to and from
Addresses on AD7–AD0 are latched by the
These multiplexed lines
Product Specification
General Description
9