z85c30 ZiLOG Semiconductor, z85c30 Datasheet - Page 38
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z85c30
Manufacturer Part Number
z85c30
Description
Cmos Scc Serial Communications Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z85C30.pdf
(71 pages)
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PS011705-0608
Z85C30 Timing
The SCC generates internal control signals from the WR and RD that are related to PCLK.
PCLK has no phase relationship with WR and RD, the circuitry generating the internal
control signals provides time for meta-stable conditions to disappear. This gives rise to a
recovery time related to PCLK. The recovery time applies only between bus transactions
involving the SCC.
The recovery time required for proper operation is specified from the falling edge of WR
or RD in the first transaction involving the SCC to the falling edge of WR or RD in the
second transaction involving the SCC. This time must be at least 3 PCLKs regardless of
which register or channel is being accessed.
The Z85C30 timings are described below:
•
•
•
Read Cycle Timing
Write Cycle Timing
Interrupt Acknowledge Cycle Timing
CMOS SCC Serial Communications Controller
Product Specification
Functional Description
34