z85c30 ZiLOG Semiconductor, z85c30 Datasheet - Page 31

• Manufacturer Part Number: z85c30
• Description: Cmos Scc Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

Programming
PS011705-0608
Z85C30
The sequence for operation of the byte count and FIFO logic is to read the registers in the
following order. RR7, RR6, and RR1 (reading RR6 is optional). Additional logic prevents
the FIFO from being emptied by multiple reads from RR1. The read from RR7 latches the
FIFO empty/full status bit (D6) and steers the status multiplexer to read from the SCC
megacell instead of the status FIFO (since the status FIFO is empty). The read from RR1
allows an entry to be read from the FIFO (if the FIFO was empty, logic was added to
prevent a FIFO underflow condition).
Write Operation
When the end of an SDLC frame (EOF) is received and the FIFO is enabled, the contents
of the status and byte-count registers are loaded into the FIFO. The EOF signal is used to
increment the FIFO. If the FIFO overflows, RR7, bit D7 (FIFO Overflow) sets to indicate
the overflow. This bit and the FIFO control logic is reset by disabling and re-enabling the
FIFO control bit (WR15, bit 02). For details of FIFO control timing during an SDLC
frame, see
The SCC contains Write registers in each channel that are programmed by the system
separately to configure the functional personality of the channels.
In the SCC, the data registers are directly addressed by selecting a High on the D/C pin.
With all other registers (except WR0 and RR0), programming the Write registers requires
two Write operations and reading the read registers requires both a Write and a Read oper-
ation. The first write is to WR0 and contains three bits that point to the selected register.
The second write is the actual control word for the selected register, and if the second
operation is read, the selected Read register is accessed. All the SCC registers, including
the data registers, can be accessed in this fashion. The pointer bits are automatically
cleared after the Read or Write operation so that WR0 (or RR0) is addressed again.
Don’t Load
Counter On
1st Flag
Reset Byte
Counter Here
0
F
Figure
A
D
Internal Byte Strobe
Increments Counter
Figure 14. SDLC Byte Counting Detail
D
14.
D
D
C
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
C
7
0
F
CMOS SCC Serial Communications Controller
Reset
Byte Counter
0
F
A
D
Internal Byte Strobe
Increments Counter
D
D
D
C
Reset
Byte Counter
Load Counter
Into FIFO and
Increment PTR
C
7
0
F
Product Specification
Functional Description
27