mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 152

• Manufacturer Part Number: mc68hc908gr8vp
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Input/Output Ports (I/O)
16.4.3 Port C Input Pullup Enable Register
The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each
of the two port C pins. Each bit is individually configurable and requires that the data direction register,
DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRC is configured for output mode.
PTCPUE1–PTCPUE0 — Port C Input Pullup Enable Bits
16.5 Port D
Port D is an 7-bit special-function port that shares four of its pins with the serial peripheral interface (SPI)
module and three of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.
16.5.1 Port D Data Register
The port D data register (PTD) contains a data latch for each of the seven port D pins.
PTD6–PTD0 — Port D Data Bits
T2CH0 — Timer 2 Channel I/O Bits
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These writeable bits are software programmable to enable pullup devices on an input port bit.
These read/write bits are software-programmable. Data direction of each port D pin is under the control
of the corresponding bit in data direction register D. Reset has no effect on port D data.
The PTD6/T2CH0 pin is the TIM2 input capture/output compare pin. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTD6/T2CH0 pin is a timer channel I/O pin or a
general-purpose I/O pin. See
1 = Corresponding port C pin configured to have internal pullup
0 = Corresponding port C pin internal pullup disconnected
Alternative Function:
Address:
Reset:
Read:
Write:
Address:
Reset:
Read:
Write:
Figure 16-12. Port C Input Pullup Enable Register (PTCPUE)
$000E
Bit 7
0
0
$0003
Bit 7
0
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
= Unimplemented
Figure 16-13. Port D Data Register (PTD)
Chapter 22 Timer Interface Module
6
0
0
= Unimplemented
T2CH0
PTD6
6
5
0
0
T1CH1
PTD5
5
4
0
0
T1CH0
Unaffected by reset
PTD4
4
3
0
0
SPSCK
PTD3
3
(TIM).
2
0
0
PTD2
MOSI
2
PTCPUE1
1
0
PTD1
MISO
1
Freescale Semiconductor
PTCPUE0
Bit 0
0
PTD0
Bit 0
SS