mc68hc908gr8vp Freescale Semiconductor, Inc, mc68hc908gr8vp Datasheet - Page 89

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mc68hc908gr8vp

Manufacturer Part Number
mc68hc908gr8vp
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 8
Configuration Register (CONFIG)
8.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers
enable or disable these options:
8.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can
be written once after each reset. All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that these registers be written
immediately after reset. The configuration registers are located at $001E and $001F. The configuration
register may be read at anytime.
To ensure correct operation of the MCU under all operating conditions, the user must write data $1C to
address $0033 immediately after reset. This is to ensure proper termination of an unused module within
the MCU.
Freescale Semiconductor
Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles)
COP timeout period (262,128 or 8176 CGMXCLK cycles)
STOP instruction
Computer operating properly module (COP)
Low-voltage inhibit (LVI) module control and voltage trip point selection
Enable/disable the oscillator (OSC) during stop mode
Address:
On a FLASH device, the options except LVI5OR3 are one-time writeable by
the user after each reset. The LVI5OR3 bit is one-time writeable by the user
only after each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writeable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in
Reset:
Read:
Write:
$001E
Bit 7
0
0
Figure 8-1. Configuration Register 2 (CONFIG2)
MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7
= Unimplemented
6
0
0
5
0
0
NOTE
NOTE
Figure 8-1
4
0
0
3
0
0
and
Figure
2
0
0
8-2.
STOPENB
OSC-
1
0
SCIBD-
SRC
Bit 0
0
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