mc68hc908gr16 Freescale Semiconductor, Inc, mc68hc908gr16 Datasheet - Page 136

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mc68hc908gr16

Manufacturer Part Number
mc68hc908gr16
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Resets and Interrupts
A power-on reset:
13.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an overflow of the COP counter.
A COP reset sets the COP bit in the SIM reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
13.2.3.3 Low-Voltage Inhibit (LVI) Reset
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the
LVI
An LVI reset:
136
TRIPF
Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
Drives the RST pin low during the oscillator stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
Sets the POR and LVI bits in the SIM reset status register and clears all other bits in the register
Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles after the power supply voltage rises to the LVI
Drives the RST pin low for as long as V
stabilization delay
Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
Sets the LVI bit in the SIM reset status register
voltage.
1. PORRST is an internally generated power-on reset pulse.
PORRST
CGMXCLK
CGMOUT
RST PIN
OSC1
(1)
Figure 13-1. Power-On Reset Recovery
CYCLES
MC68HC908GR16 Data Sheet, Rev. 5.0
4096
CYCLES
32
DD
is below the LVI
TRIPR
voltage and during the oscillator
TRIPR
voltage
Freescale Semiconductor

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