mc68hc908jb8 Freescale Semiconductor, Inc, mc68hc908jb8 Datasheet - Page 166
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mc68hc908jb8
Manufacturer Part Number
mc68hc908jb8
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908JB8.pdf
(286 pages)
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Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Technical Data
166
V
V
DD
DD
Notes:
1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using V
2. See
V
V
DD
DD
+ V
+ V
Section 18. Electrical Specifications
HI
HI
(contain
BLANK
BLANK
$FF)
NOT
X
X
Table 10-1. Mode Entry Requirements and Options
X
X
0
1
Table 10-1
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ = V
2. If IRQ = V
3. If $FFFE & $FFFF is blank (contains $FF):
X
X
0
0
– External clock on OSC1 is 3MHz
– PTA3 = low
– External clock on OSC1 is 6MHz
– PTA3 = high
– External clock on OSC1 is 6MHz
– IRQ = V
X
X
1
1
X
1
1
1
shows the pin conditions for entering monitor mode. As
for V
Monitor ROM (MON)
External Clock,
DD
DD
DD
DD
+ V
+ V
+ V
3MHz
6MHz
6MHz
6MHz
f
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
XCLK
HI
voltage level requirements.
HI
HI
:
:
DD
Frequency,
(f
(f
(f
+ V
XCLK
XCLK
XCLK
(f
3MHz
3MHz
3MHz
3MHz
f
Bus
XCLK
BUS
HI
for monitor mode entry.
÷ 2)
÷ 2)
÷ 2)
)
High-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
Low-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
Enters user mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
Freescale Semiconductor
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