mc68hc05pv8 Freescale Semiconductor, Inc, mc68hc05pv8 Datasheet - Page 68

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mc68hc05pv8

Manufacturer Part Number
mc68hc05pv8
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
T echnical Data
Technical Data
Port C Contact Sense/HV
and Port C Short circuit
Voltage, Temperature
Port A High Nibble
Port A Low Nibble
Function
Interrupts
Interrupt
Interrupt
Inputs
The M68HC05 CPU does not support interruptible instructions,
therefore, the maximum latency to the first instruction of the interrupt
service routine must include the longest instruction execution time plus
stacking overhead.
Latency = (Longest instruction execution time + 10) x t
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the register contents to
be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place.
Figure 4-1
processing.
Table 4-1 Reset/Interrupt Vector Addresses
Freescale Semiconductor, Inc.
For More Information On This Product,
Port A4–7
Port A0–3
Source
HTI Bit
HVI Bit
LVI Bit
SCIF6
SCIF5
CSIF
shows the sequence of events that occur during interrupt
Go to: www.freescale.com
Interrupts
PAHIE Bit
PALIE Bit
HTIM Bit
HVIM Bit
LVIM Bit
SCIE6
SCIE5
Local
Mask
CSIE
Global
Mask
I-Bit
I-Bit
I-Bit
(1 = Highest)
MC68HC(8)05PV8/A — Rev. 1.9
Priority
5
6
7
CYC
$3FF4–$3FF5
$3FF2–$3FF3
$3FF0–$3FF1
Address
Vector

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