mc68hc05pv8 Freescale Semiconductor, Inc, mc68hc05pv8 Datasheet - Page 71

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mc68hc05pv8

Manufacturer Part Number
mc68hc05pv8
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC(8)05PV8/A — Rev. 1.9
the CPU is pushed onto the stack and the I-bit is set. This masks further
interrupts until the present one is serviced. The interrupt service routine
address is specified by the contents of memory locations $3FFA and
$3FFB.
INTP, INTN – External interrupt sensitivity options
INTE – External interrupt enable
The INTE bit can be written to only while the I-bit is set, and is set by
power-on or external reset, thus enabling the external interrupt function.
$000A
Reset:
Read:
Write:
These two bits allow the user to select which edge of the IRQ pin is
sensitive as shown in
the I-bit is set, and are cleared by power-on or external reset.
Therefore the device is initialized with negative edge and low level
sensitivity.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = External interrupt function (IRQ) enabled.
0 = External interrupt function (IRQ) disabled.
POR
Bit 7
Figure 4-2 System Control Register (SYSCTRL)
NA
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INTP
0
0
1
1
INTP
6
0
Interrupts
INTN
Table 4-2 IRQ sensitivity
0
1
0
1
INTN
Table
5
0
4-1. Both bits can be written only while
Negative edge and low level
Positive and negative edge
INTE
4
0
Negative edge only
Positive edge only
IRQ sensitivity
sensitive
sensitive
WCOP
3
0
WCP
2
0
External Interrupt (IRQ)
FPIE
1
0
Technical Data
Interrupts
FPICLK
Bit 0
0

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