mc68hc11e0fnr2 Freescale Semiconductor, Inc, mc68hc11e0fnr2 Datasheet - Page 120

• Manufacturer Part Number: mc68hc11e0fnr2
• Description: Hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats. The clock phase and polarity should be identical
for the master SPI device and the communicating slave device. In some cases, the phase and polarity
are changed between transfers to allow a master device to communicate with peripheral slaves having
different requirements.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial byte.
Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
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Serial Peripheral Interface (SPI)
÷2 ÷4 ÷16 ÷32
MCU CLOCK
INTERNAL
SELECT
DIVIDER
SPI STATUS REGISTER
SPI CONTROL
SPI INTERRUPT
REQUEST
M68HC11E Family Data Sheet, Rev. 5.1
Figure 8-1. SPI Block Diagram
MSB
8--BIT SHIFT REGISTER
INTERNAL
DATA BUS
MSTR
SPE
READ DATA BUFFER
SPI CONTROL REGISTER
CLOCK
LOGIC
LSB
CLOCK
S
M
M
S
S
M
Freescale Semiconductor
MISO
MOSI
PD2
PD3
SCK
PD4
PD5
SS