mc68ec030 Freescale Semiconductor, Inc, mc68ec030 Datasheet - Page 14

• Manufacturer Part Number: mc68ec030
• Description: Second-generation 32-bit Enhanced Embedded Controller
• Manufacturer: Freescale Semiconductor, Inc

ASYNCHRONOUS TRANSFERS
1 4
thereby increasing possible performance. Burst mode transfers can be used to fill lines of the instruction
and data caches when the MC68EC030 asserts cache burst request (
cycle with
until the burst is completed. Use of this mode can further increase the available bus bandwidth in systems
that use DRAMs with page, nibble, or static-column mode operation.
Though the MC68EC030 has a full 32-bit data bus, it offers the ability to automatically and dynamically
downsize its bus to 8 or 16 bits if peripheral devices are unable to accommodate the entire 32 bits. This
feature allows the programmer to write code that is not bus-width specific. For example, long-word (32 bit)
accesses to peripherals may be used in the code; yet, the MC68EC030 will transfer only the amount of
data that the peripheral can manage. This feature allows the peripheral to define its port size as 8, 16, or
32 bits wide, and the MC68EC030 will dynamically size the data transfer accordingly, using multiple bus
cycles when necessary. Hence, programmers are not required to program for each device port size or
know the specific port size before coding; hardware designers have the flexibility to choose hardware
implementations regardless of software implementations.
The dynamic bus sizing mechanism is invoked by
example, if the controller is executing an instruction that requires reading a long-word operand, it will
attempt to read 32 bits during the first bus cycle to a long-word address boundary. If the port responds
that it is 32 bits wide, the MC68EC030 latches all 32 bits of data and continues. If the port responds that it
is 16 bits wide, the MC68EC030 latches the 16 valid bits of data and continues. An 8-bit port is handled
similarly but has four bus read cycles. Each port is fixed in the assignment to particular sections of the data
bus. However, the MC68EC030 has no restrictions concerning the alignment of operands in memory;
long-word operands need not be aligned to long-word address boundaries. When misaligned data
requires multiple bus cycles, the MC68EC030 automatically runs the minimum number of bus cycles.
Instructions must still be aligned to word boundaries.
The timing of asynchronous bus cycles is also determined by the assertion of
cycle basis. If the
appropriate setup time), the cycle terminates in the minimum amount of time (corresponding to three-
clock-cycle total). The cycle can be lengthened by delaying
one-clock increments) until the device being accessed is able to terminate the cycle. This flexibility gives
the controller the ability to communicate with devices of varying speeds while operating at the fastest rate
possible for each device.
The asynchronous transfer mechanism allows external errors to abort cycles upon the assertion of bus
error (
HALT
BERR)
.
STERM
or allows individual bus cycles to be retried with the simultaneous assertion of
DSACKx
, subsequent cycles may accept data on every clock cycle where
signals are valid 1.5 clocks after the beginning of the bus cycle (with the
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DSACKx
DSACKx
and occurs on a cycle-by-cycle basis. For
CBREQ
(effectively inserting wait states in
). After completing the first
DSACKx
STERM
on a cycle-by-
M O T O R O L A
is asserted
BERR
and