mpc8308 Freescale Semiconductor, Inc, mpc8308 Datasheet - Page 57
mpc8308
Manufacturer Part Number
mpc8308
Description
Mpc8308 Powerquicc Ii Pro Processor Hardware Specification
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8308.pdf
(88 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
mpc8308CVMADD
Manufacturer:
Freescale
Quantity:
170
Company:
Part Number:
mpc8308CVMADD
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
mpc8308CVMADD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8308CVMADDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8308CVMAFD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8308CVMAFDA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8308CVMAGD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8308CVMAGDA
Manufacturer:
FREESCAL
Quantity:
329
Part Number:
mpc8308CVMAGDA
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
mpc8308CZQAFD
Manufacturer:
FREESCAL
Quantity:
717
Company:
Part Number:
mpc8308VMADD
Manufacturer:
Freescale
Quantity:
152
All values refer to V
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including hysteresis)
Noise margin at the HIGH level for each connected device (including hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
5. The device does not follow the I
Figure 45
Figure 46
Freescale Semiconductor
inputs and t
with respect to the time data input signals (D) reach the valid state (V) relative to the t
(H) state or setup time. Also, t
went invalid (X) relative to the t
(I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
(K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
undefined region of the falling edge of SCL.
B
SDA
= capacitance of one bus line in pF.
SCL
provides the AC test load for the I
shows the AC timing diagram for the I
(first two letters of functional block)(reference)(state)(signal)(state)
S
IH
I2DXKL
(min) and V
t
I2CF
t
I2CL
t
I2SXKL
has only to be met if the device does not stretch the low period (t
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Output
IL
(max) levels (see
Table 44. I
I2SXKL
I2C
2
C-BUS Specifications, Version 2.1, regarding the t
clock reference (K) going to the low (L) state or hold time. Also, t
Parameter
symbolizes I
Figure 46. I
t
I2DXKL
2
C AC Electrical Specifications (continued)
Table
Figure 45. I
Z
t
I2DVKH
0
2
= 50 Ω
43).
C timing (I2) for the time that the data with respect to the start condition (S)
t
I2CH
2
2
C.
C Bus AC Timing Diagram
t
2
I2SXKL
2
C bus.
C AC Test Load
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. For example, t
Sr
t
I2SVKH
t
I2KHKL
R
L
= 50 Ω
I2CF
I2C
IHmin
t
I2CL
AC parameter.
Symbol
I2PVKH
clock reference (K) going to the high
t
t
I2PVKH
NV
I2KHDX
V
V
I2DVKH
) of the SCL signal.
of the SCL signal) to bridge the
NH
NL
DD
t
I2CR
/2
I2PVKH
1
symbolizes I
0.1 × NV
0.2 × NV
P
symbolizes I
Min
0.6
1.3
t
I2CF
I2C
DD
DD
clock reference
2
C timing (I2)
S
Max Unit
—
—
—
—
2
C timing
for
μs
μs
V
V
I
57
2
C