mpc8308 Freescale Semiconductor, Inc, mpc8308 Datasheet - Page 9

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mpc8308

Manufacturer Part Number
mpc8308
Description
Mpc8308 Powerquicc Ii Pro Processor Hardware Specification
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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5.2
Table 11
Table 12
Freescale Semiconductor
Required assertion time of HRESET (input) to activate reset flow
Required assertion time of PORESET with stable power and clock applied to
SYS_CLK_IN
HRESET assertion (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with
respect to negation of PORESET
Input hold time for POR configuration signals with respect to negation of HRESET
Time for the device to turn off POR configuration signal drivers with respect to the
assertion of HRESET
Time for the device to turn on POR configuration signal drivers with respect to the
negation of HRESET
Notes:
1. t
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]
SYS_CLK_IN
provides the reset initialization AC timing specifications.
provides the PLL lock times.
RESET AC Electrical Characteristics
System PLL lock time
e300 core PLL lock time
is the clock period of the input clock applied to SYS_CLK_IN
Output low voltage
Output low voltage
Parameter/Condition
Characteristic
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Table 10. RESET Pins DC Electrical Characteristics (continued)
Parameter/Condition
Table 11. RESET Initialization Timing Specifications
Symbol
V
V
OL
OL
Table 12. PLL Lock Times
Min
I
I
OL
OL
Condition
= 3.2 mA
= 8.0 mA
Max
100
100
Min
Min
512
32
32
4
0
1
Unit
μs
μs
Max
0.5
0.4
Max
4
Unit
t
t
t
t
Notes
V
V
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
RESET Initialization
Unit
ns
ns
ns
Notes
1, 2
1
1
2
9

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