mpc89x51a Megawin Technology, mpc89x51a Datasheet - Page 15

• Manufacturer Part Number: mpc89x51a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

TF2: Timer2 overflow flag. It will be set by a Timer2 overflow and must be cleared by software.
EXF2: Timer2 external flag. It will be set when either a capture or reload is caused by a negative transition
TCLK: When set causes the serial port to use Timer2 overflow pulse for its transmit clock in mode 1 and
IE1
EXEN2: Timer-2 external enable flag. When set, allows a capture or reload to occur. As a result of a
T2OE: Timer 2 Output Enable bits. It enables Timer2 overflow rate to toggle P1.0.
DCEN: Down Count Enable bits. When set, this allows Timer2 to be configured as a down counter.
SFR: TCON
TF1: =Timer1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
TR1: =Timer1 run control bits. Set/Cleared by software.
TF0: =Timer0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
TR0: =Timer1 run control bits. Set/Cleared by software.
IT1
IE0
IT0
SFR: T2MOD
SFR: T2CON
RCLK: When set causes the serial port to use Timer2 overflow pulse for its receive clock in mode and
TR2: Start/Stop control for Timer2.
MEGAWIN
Bits-7
Bits-7
Bits-7
: =Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when
TF1
: =Interrupt 1 type control bits. Set/Cleared by software to specified falling edge/low level triggered
: =Interrupt 0 type control bits. Set/Cleared by software to specified falling edge/low level triggered
TF2
: =Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when
TF2 will not be set when either TCLK or RCLK =1.
on pin T2EX and EXEN2=1. When Timer2 interrupt is enabled, EXF2=1 will cause the CPU to
vector to the timer2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in Auto-Reload Up-Down mode (ARUD).
mode 3. RCLK=0 causes Timer1 overflow pulse to be used.
interrupt processed.
processor vectors to the interrupt routine, or clearing the bits in software.
interrupt.
interrupt.
mode 3. RCLK=0 causes Timer1 overflow pulse to be used.
interrupt processed.
processor vectors to the interrupt routine, or clearing the bits in software.
EXEN2=0 causes Timer2 to ignore events at T2EX.
negative transition on T2EX if Timer2 is not being used to clock the serial port.
Bits-6
Bits-6
Bits-6
EXF2
TR1
RCLK
Bits-5
Bits-5
Bits-5
TF0
TCLK
Bits-4
Bits-4
Bits-4
TR0
MPC89x51A Data Sheet
EXEN2
Bits-3
Bits-3
Bits-3
IE1
Bits-2
Bits-2
Bits-2
TR2
IT1
T2OE
Bits-1
Bits-1
Bits-1
C//T2
IE0
CP/RL2
DCEN
Bits-0
Bits-0
Bits-0
IT0
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