mpc89x51a Megawin Technology, mpc89x51a Datasheet - Page 30

• Manufacturer Part Number: mpc89x51a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

ISPEN: ISP function enabling bits
SWBS: Secondary Booting program selecting
SWRST: software reset trigger
SFR: SCMD (Sequential Command Data register for ISP) :
SFR: ISPCR (ISP Control register):
Procedures demonstrating ISP function
Notice: Software reset actions could reset other SFR, but it never influences
WAIT: Waiting time selection while the flash is busy.
SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if
ISPCR.7 = 1, ISP activity will be triggered.
When this register is read, the device ID of MPC89x51A will be returned (2 bytes). The MSB bytes of DID
is F0h and LSB bytes 01h. IFADRL[0] is used to select HIGH/LOW bytes of DID.
30
Bits-7
Bits-7
ISPCR[2:0]
ISPEN
0 0 0
0 0 1
0 1 0
0 1 1
0: = Disable ISP program to change flash
1: = Enable ISP program to change flash
0: = Boot from main-memory.
1: = Boot from ISP memory.
1: = Generate software system reset. It will be cleared by hardware automatically.
SWBS. The ISPEN and SWBS only will be reset by power-up action, not software reset.
0: = No operation
SWBS
Bits-6
Bits-6
IFMT ← xxxxx011
ISPCR ← 100xx010
IFADRH ← (page address high byte)
IFADRL ← (page address low byte)
SCMD ← 46h
SCMD ← B9h
(CPU progressing will be hold here )
(CPU continues)
Page Erase
43769
21885
10942
SWRST
5471
Bits-5
Bits-5
b
ISP-Command (Device ID)
b
MPC89x51A Data Sheet
Bits-4
Bits-4
-
CPU Wait time (Machine Cycle)
Program
240
120
60
30
Erase a specific flash page
Bits-3
Bits-3
-
/* set ISPEN=1 to enable flash change.
/* specify the address of the page to be erased */
/* choice page-erasing command */
set WAIT=010, 10942 MC; assumed 10M X’s*/
/* trig ISP activity */
Bits-2
Bits-2
Read
43
22
11
6
Bits-1
Bits-1
WAIT
Recommended
System clock
40M
20M
10M
5M
Bits-0
bits ISPEN
Bits-0
MEGAWIN
and