mpc5553 Freescale Semiconductor, Inc, mpc5553 Datasheet - Page 64

• Manufacturer Part Number: mpc5553
• Description: Mpc5553 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MPC5553 Revision History
64
Revision
Rev 2.0
Rev 2.0
Author
NH
NH
02/07/07
2/09/07
Date
Table 33. MPC5553 Revision History (continued)
MPC5553 Microcontroller Data Sheet, Rev. 2.0
Changes per RD sign-off review:
Table 22
Removed references to CAL_OE, CAL_RD_WR, and CAL_TS because they really use
the EBI signals OE, RD_WR, and TS on the MPC5553.
• Changed paragraph preceding
•
•
• Corrected the following EBI signals:
•
To:
Section 3.7.1, “Input Value of Pins During POR Dependent on
From:
Table 22
Added the correct pins to the calibration signals:
CAL_ADDR[10:11, 27:30], CAL_WE/BE[0:1], CAL_CS[0, 2:3], and
CAL_DATA[0:15]. Added calibration signals to Specs 5 and 8.
Specs 7 and 8: Added the following signals to Specs 7 and 8 the EBI section: OE,
RD_WR, and BDIP. Broke out Spec 6 CLKOUT Posedge to output signal valid into
Spec 6 for the EBI signals, and Spec 6a for the calibration signals, Broke out Spec 7
Input Signal Valid to CLKOUT Posedge into Spec 7 for the EBI signals, and Spec 7a
for the calibration signals.
Section 3.7.3, “Power-Down Sequence (VRC33
in ORed_POR to become ORed POR.
From: Although there are no power up/down sequencing requirements to prevent
Pad:
To: There are no power up/down sequencing requirements to prevent issues such
To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and
RSTCFG are not treated as ones (1s) when POR negates, VDD33 must not lag
VDDSYN and the RESET pin power (VDDEH6) when powering the device by
more than the VDD33 lag specification in
either VDDSYN or the RESET power pin (VDDEH6) by more than the VDD33 lag
specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot
lag both by more than the VDD33 lag specification. This VDD33 lag specification
only applies during power up. VDD33 has no lead or lag requirements when
powering down.
When powering the device, VDD33 must not lag VDDSYN and the RESET power
pin (VDDEH6) by more than the VDD33 lag specification listed in
avoids accidentally selecting the bypass clock mode because the internal versions
of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the
default state when POR negates. VDD33 can lag VDDSYN or the RESET power
pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This
VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.
issues like latch-up, excessive current spikes, etc., the state of the I/O pins during
power up/down varies depending on power. Prior to exiting POR, the pads are in
a high impedance state (Hi-Z).
as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O
pins during power up/down varies depending on which supplies are powered.
Bus Operation Timing:
Bus Operation Timing:
Substantive Change(s)
Table 7
Power Sequence Pin Status for the Fast
Table
Grounded)” Deleted the underscore
6. VDD33 individually can lag
Freescale Semiconductor
VDD33,” changed
Table
6. This