tspc860 ATMEL Corporation, tspc860 Datasheet - Page 55
tspc860
Manufacturer Part Number
tspc860
Description
Integrated Communication Processor
Manufacturer
ATMEL Corporation
Datasheet
1.TSPC860.pdf
(93 pages)
- Current page: 55 of 93
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Table 12. RESET Timing
Figure 36. Reset Timing
2129B–HIREL–12/04
Num
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
Characteristic
CLKOUT to HRESET high impedance
CLKOUT to SRESET high impedance
RSTCONF pulse width
–
Configuration Data to HRESET rising edge
set up time
Configuration Data to RSTCONF rising
edge set up time
Configuration Data hold time after
RSTCONF negation
Configuration Data hold time after HRESET
negation
HRESET and RSTCONF asserted to Data
out drive
RSTCONF negated to Data out high
impedance.
CLKOUT of last rising edge before chip
tristates HRESET to Data out high
impedance.
DSDI, DSCK set up
DSDI, DSCK hold time
SRESET negated to CLKOUT rising edge
for DSDI and DSCK sample
D[0:31] (IN)
RSTCONF
HRESET
–
Configuration from Data Bus
R71
R74
R73
515.15
504.55
242.42
90.91
Min
350
–
–
–
0
0
–
–
–
0
33 MHz
Max
R75
20
20
25
25
25
–
–
–
–
–
–
–
–
–
Min
425
425
350
200
75
–
–
–
0
0
–
–
–
0
40 MHz
R76
Max
20
20
25
25
25
–
–
–
–
–
–
–
–
Min
340
350
350
160
60
–
–
–
0
0
–
–
–
0
50 MHz
Max
20
20
25
25
25
–
–
–
–
–
–
–
–
–
257.58
277.27
121.21
45.45
Min
350
–
–
–
0
0
–
–
–
0
66 MHz
Max
20
20
25
25
25
–
–
–
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
55
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