tspc860 ATMEL Corporation, tspc860 Datasheet - Page 80
tspc860
Manufacturer Part Number
tspc860
Description
Integrated Communication Processor
Manufacturer
ATMEL Corporation
Datasheet
1.TSPC860.pdf
(93 pages)
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Table 27. I
Notes:
Figure 73. I
80
Num
200
200
202
203
204
205
206
207
208
209
210
211
1. SCL frequency is given by SCL = BrgClk_frequency/((BRG register + 3) × pre_scaler
TSPC860 [Preliminary]
The ratio SYNCCLK/(BRG_CLK/pre_scaler) must be greater or equal to 4/1.
SDA
SCL
2
2
C AC Electrical Specifications – SCL > 100 kHz
C Bus Timing Diagram
Characteristic
SCL Clock Frequency (SLAVE)
SCL Clock Frequency (MASTER)
Bus Free Time Between Transmissions
LOW Period of SCL
HIGH Period of SCL
START Condition Setup Time
START Condition Hold Time
DATA Hold Time
DATA Setup Time
SDL/SCL Rise Time
SDL/SCL Fall Time
STOP Condition Setup Time
202
205
206
(1)
203
207
209
Expression
fSCL
fSCL
204
BRGCLK/16512
1/2(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(2.2 × fSCL)
1/(40 × fSCL)
210
Min
–
–
0
0
208
1/(10 × fSCL)
1/(33 × fSCL)
BRGCLK/48
BRGCLK/48
Max
211
–
–
–
–
–
–
–
–
2129B–HIREL–12/04
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
s
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