dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 48

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

15 0 Switching Characteristics
Note 1 ACK is not generated until CS and SRD are low and the SNIC has synchronized to the register access The SNIC will insert an integral number of Bus Clock
cycles until it is synchronized In Dual Bus systems additional cycles will be used for a local or remote DMA to complete Wait states must be issued to the CPU until
ACK is asserted low
Note 2 CS may be asserted before or after SRD If CS is asserted after SRD rackl is referenced from falling edge of CS CS can be de-asserted concurrently with
SRD or after SRD is de-asserted
Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention
Symbol
rss
rsh
aswi
ackdv
rdz
rackl
rackh
rsrsl
Register Select Setup to ADS0 Low
Register Select Hold from ADS0 Low
Address Strobe Width In
Acknowledge Low to Data Valid
Read Strobe to Data TRI-STATE (Note 3)
Read Strobe to ACK Low (Notes 1 2)
Read Strobe to ACK High
Register Select to Slave Read Low
Latched RS0 – 3
Parameter
Register Read (Latched Using ADS0)
AC Specs DP83901A Note All Timing is Preliminary
48
Min
10
13
15
15
10
n bcyc
Max
55
70
30
a
30
TL F 10469 – 32
Units
ns
ns
ns
ns
ns
ns
ns
ns