lm4550 National Semiconductor Corporation, lm4550 Datasheet
lm4550
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lm4550 Summary of contents
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... Headphone Amplifier, Sample Rate Conversion and National 3D Sound General Description The LM4550 is an audio codec for PC systems which is fully PC99 compliant and performs the analog intensive functions of the AC97 Rev2.1 architecture. Using 18-bit Sigma-Delta A/D’s and D/A’s, the LM4550 provides Dynamic Range ...
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... CD Input to Line Output, -60dB Input THD+N, A-Weighted V = -3dB 1kHz 10kΩ Left to Right CD Left to Right 0dB to 22.5dB +12dB to -34.5dB 3 ≤ T −40˚C ≤ MAX 4.2V ≤ 3.0V ≤ 5V 5V LM4550 Typical Limit (Note 7) (Note 8) 4.2 5.5 3.0 5 500 30 2. 0.01 0.02 1 0.1 1 -95 ...
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... AC Link outputs Variation of BIT_CLK period from 50% duty cycle SDATA_IN, SDATA_OUT to falling edge of BIT_CLK Hold time of SDATA_IN, SDATA_OUT from falling edge of BIT_CLK BIT_CLK, SYNC, SDATA_IN or SDATA_OUT Units LM4550 (Limits) Typical Limit (Note 7) (Note 8) 18 Bits (min) 20 kHz 18 Bits ...
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... SDATA_OUT For cold reset For warm reset For warm reset For ATE Test Mode For ATE Test Mode –T )/θ or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4550 5V 5V 25˚C. The reference for 0dB is 1Vrms unless ...
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Timing Diagrams www.national.com Clocks 10097210 Data Setup and Hold 10097211 Digital Rise and Fall 10097212 Cold Reset Warm Reset 6 10097213 10097214 ...
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... Typical Application FIGURE 1. LM4550 Typical Application Circuit for a Single Codec Application when inputs are at 1 Vrms. 7 10097203 www.national.com ...
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... The amount of VIDEO_L VIDEO_L 16 I signal mixed in the left output stream can be adjusted from +12dB to −34.5dB in 1.5dB steps as well as muted via register 14h. Top View Order Number LM4550VH See NS Package Number VBH48A ANALOG I/O 9 10097202 www.national.com ...
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Pin Descriptions (Continued) Name Pin Functional Description This line level input can be routed through the Input Mux and recorded by the right ADC. In addition, this analog input gets summed into the right output stream. The ...
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... Codec. This data stream contains both control data and ADC audio data. This output is clocked out SDATA_IN the LM4550 on the rising edge of BIT_CLK. 48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT SYNC 10 I serial streams. SYNC must be synchronous to BIT_CLK. ...
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Pin Descriptions (Continued) Name Pin This pin is not used and should be left open (NC). However, a capacitor to ground on this pin AFILT2 permitted - it will not affect performance. These pins ...
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Typical Performance Characteristics DAC Frequency Response Headphone Amplifier THD+N vs Frequency (Continued) 10097220 10097227 13 Headphone Amplifier Noise Floor 10097226 Headphone Amplifier THD+N vs Output Power 10097228 www.national.com ...
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... The first bit of slot 0 is designated the "Valid Frame" bit. If this bit indicates that the current data frame contains at least one slot of valid data and the LM4550 will further sample the next four bits and slots 7 & 8 and 6 & www ...
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... Reserved SDATA_OUT Slot 2: Control Data Slot 2 is used to transmit 16 bit control data to the LM4550 in the event that the current operation is a write operation. The least significant four bits should be stuffed with zeros by the AC ’97 controller. If the current operation is a register read, (Continued) the entire slot, bits 19 through 0 should be stuffed with zeros ...
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... Digital Controller samples SDATA_IN on the falling edge of BIT_CLK. The LM4550 will continue outputting the SDATA_IN stream on each successive rising edge of BIT- _CLK. The LM4550 outputs data MSB first MSB justi- fied format. All reserved bits and slots are stuffed with "0" ’s by the LM4550. ...
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... Writing any value to this register causes a register reset which changes all of the registers back to their default val- ues read is performed on this register, the LM4550 will return a value of 0D50h indicating that National 3D Sound is implemented, 18bit data is supported for both the ADC’s and DAC’ ...
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... LPBK Powerdown Control / Status Register (26h) This read/write register is used to monitor subsystem readi- ness and also to program the LM4550 powerdown states. The lower half of this register is read only with a "1", indicat- ing the subsection is ready. Writing to the lower 8 bits will have no effect. When the AC Link " ...
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... Application Information Extended Audio ID Register (28h) This read only register identifies which AC97 Extended Au- dio features are supported. The LM4550 features AMAP (Slot/DAC mappings based on codec ID), VRA (Variable Pin46 (ID1) Pin45 (ID0) NC (not connected) NC (not connected) NC/DV NC/DV DD NC/DV GND DD GND NC/DV GND GND Extended Audio Status/Control Register (2Ah) This read/write register provides status and control of the Variable Sample Rate function ...
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AC’97 2.1 Multiple Codec Secondary Codec Register Access Definitions By definition there can be one Primary Codec (ID00) and up to three Secondary Codecs (ID01, 10, and 11). The Codec ID functions as a chip select. Secondary devices are individually ...
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Secondary Codec Register Access Definitions Reg 28h & Multiple Codec Option: Reg Name D15 D14 D13 D12 28h Extended ID1 ID0 x Audio ID The AMAP bit the Extended Audio ID Register (registers 28h), indicates whether or not ...
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Secondary Codec www.national.com 24 10097224 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted 48-Lead , LQFP 1.4mm, JEDEC (M) Order Number LM4550VH NS Package Number VBH48A 2. A critical component is any component of a life ...