sc18is602 NXP Semiconductors, sc18is602 Datasheet - Page 11

• Manufacturer Part Number: sc18is602
• Description: Sc18is602/sc18is603 I?c-bus To Spi Bridge
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC18IS602_603_3
Product data sheet
7.1.11.2 Open-drain output configuration
A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin
contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the
primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is
pulled LOW by an external device, the weak pull-up turns off, and only the very weak
pull-up remains on. In order to pull the pin LOW under these conditions, the external
device has to sink enough current to overpower the weak pull-up and pull the pin below its
input threshold voltage.
The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
LOW-to-HIGH transitions on a quasi-bidirectional pin when the port latch changes from a
logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks
quickly pulling the pin HIGH.
The quasi-bidirectional pin configuration is shown in
Although the SC18IS602/603 is a 3 V device, most of the pins are 5 V tolerant. If 5 V is
applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from
the pin to V
configured in quasi-bidirectional mode is discouraged.
A quasi-bidirectional pin has a Schmitt-triggered input that also has a glitch suppression
circuit.
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the pin when the port latch contains a logic 0. To be used as a logic output, a
pin configured in this manner must have an external pull-up, typically a resistor tied to
V
The open-drain pin configuration is shown in
An open-drain pin has a Schmitt-triggered input that also has a glitch suppression circuit.
Fig 16. Quasi-bidirectional output configuration
DD
. The pull-down for this mode is the same as for the quasi-bidirectional mode.
pin latch data
DD
causing extra power consumption. Therefore, applying 5 V to pins
Rev. 03 — 13 August 2007
2 SYSTEM
CYCLES
CLOCK
Figure
P
input data
V
SS
strong
17.
Figure
P
SC18IS602/603
very
weak
16.
P
glitch rejection
I
2
C-bus to SPI bridge
weak
© NXP B.V. 2007. All rights reserved.
V
DD
002aac548
GPIO pin
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