isp1505a NXP Semiconductors, isp1505a Datasheet - Page 75

• Manufacturer Part Number: isp1505a
• Description: Isp1505a; Isp1505c Ulpi Hi-speed Universal Serial Bus Host And Peripheral Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. LINESTATE[1:0] encoding for upstream
Table 11. LINESTATE[1:0] encoding for downstream
Table 12. V
Table 13. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .32
Table 14. Link decision times . . . . . . . . . . . . . . . . . . . . .33
Table 15. Register map overview . . . . . . . . . . . . . . . . . .45
Table 16. Vendor ID Low register (address R = 00h)
Table 17. Vendor ID High register (address R = 01h)
Table 18. Product ID Low register (address R = 02h)
Table 19. Product ID High register (address R = 03h)
Table 20. Function Control register
Table 21. Function Control register
Table 22. Interface Control register
Table 23. Interface Control register
Table 24. OTG Control register
Table 25. OTG Control register
Table 26. USB Interrupt Enable Rising Edge register
Table 27. USB Interrupt Enable Rising Edge register
ISP1505A_ISP1505C_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ULPI signal description . . . . . . . . . . . . . . . . . .14
Signal mapping during low-power mode . . . . .15
Signal mapping for 6-pin serial mode . . . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and resistor settings . . . . . . .17
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .23
RXCMD byte format . . . . . . . . . . . . . . . . . . . . .24
facing ports: peripherals . . . . . . . . . . . . . . . . .25
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .26
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .27
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
bit description . . . . . . . . . . . . . . . . . . . . . . . . .46
bit description . . . . . . . . . . . . . . . . . . . . . . . . .46
bit description . . . . . . . . . . . . . . . . . . . . . . . . .46
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .46
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit description . . . . . . . . . . . . . . . . . .47
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .47
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit description . . . . . . . . . . . . . . . . . .48
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .48
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit description . . . . . . . . . . . . . . . . . .49
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit allocation . . . . . . . . . . . . . . . . . . .49
BUS
indicators in RXCMD for typical
Rev. 01 — 19 October 2006
Table 28. USB Interrupt Enable Falling Edge register
Table 29. USB Interrupt Enable Falling Edge register
Table 30. USB Interrupt Status register
Table 31. USB Interrupt Status register
Table 32. USB Interrupt Latch register
Table 33. USB Interrupt Latch register
Table 34. Debug register (address R = 15h)
Table 35. Debug register (address R = 15h)
Table 36. Scratch register (address R = 16h to 18h,
Table 37. Power Control register (address R = 3Dh to 3Fh,
Table 38. Power Control register (address R = 3Dh to 3Fh,
Table 39. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 40. Recommended operating conditions . . . . . . . . 55
Table 41. Static characteristics: supply pins . . . . . . . . . . 56
Table 42. Static characteristics: digital pins (CLOCK, DIR,
Table 43. Static characteristics: pin V
Table 44. Static characteristics: analog I/O pins
Table 45. Static characteristics: V
Table 46. Static characteristics: V
Table 47. Static characteristics: resistor reference . . . . . 59
Table 48. Dynamic characteristics: reset and clock . . . . 60
Table 49. Dynamic characteristics: digital I/O pins . . . . . 61
Table 50. Dynamic characteristics: analog I/O pins
Table 51. Recommended bill of materials . . . . . . . . . . . . 65
Table 52. SnPb eutectic process (from J-STD-020C) . . . 71
Table 53. Lead-free process (from J-STD-020C) . . . . . . 71
Table 54. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 55. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73
ULPI HS USB host and peripheral transceiver
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh,
C = 0Fh) bit description . . . . . . . . . . . . . . . . . . 50
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit allocation . . . . . . . . . . . . . . . . . . . 50
(address R = 10h to 12h, W = 10h, S = 11h,
C = 12h) bit description . . . . . . . . . . . . . . . . . . 50
(address R = 13h) bit allocation . . . . . . . . . . . 50
(address R = 13h) bit description . . . . . . . . . . 51
(address R = 14h) bit allocation . . . . . . . . . . . 51
(address R = 14h) bit description . . . . . . . . . . 51
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 51
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 52
W = 16h, S = 17h, C = 18h) bit description . . . 52
W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 52
W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 53
STP, NXT, DATA[7:0], RESET_N/PSW_N) . . . 56
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ISP1505A; ISP1505C
BUS
BUS
BUS
comparators . . . . 59
resistors . . . . . . . . 59
© NXP B.V. 2006. All rights reserved.
/FAULT . . . . . . 57
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