isp1704a NXP Semiconductors, isp1704a Datasheet - Page 32

• Manufacturer Part Number: isp1704a
• Description: Ulpi Hi-speed Usb Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 21.
Table 22.
ISP1704A_1
Product data sheet
Bit
7
6
5
4 to 3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
-
SUSPENDM
RESET
OPMODE[1:0]
TERMSELECT
XCVRSELECT
[1:0]
FUNC_CTRL - Function Control register (address R = 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit allocation
PROT_DIS
R/W/S/C
10.6 INTF_CTRL register
INTF_
7
0
The INTF_CTRL register enables alternative interfaces. All of these modes are optional
features provided for legacy link cores. Setting more than one of these fields results in
undefined behavior.
Description
reserved
Suspend LOW: Active-LOW PHY suspend.
Places the PHY into low-power mode. The PHY will power-down all blocks, except the full-speed
receiver, OTG comparators and ULPI interface pins.
To come out of low-power mode, the link must assert STP. The PHY will automatically clear this
bit when it exits low-power mode.
0b — Low-power mode
1b — Powered
Reset: Active-HIGH transceiver reset.
After the link sets this bit, the PHY will assert DIR and reset the digital core. This does not reset
the ULPI interface or the ULPI register set.
When the reset is completed, the PHY will deassert DIR and automatically clear this bit, followed
by an RXCMD update to the link.
The link must wait for DIR to deassert before using the ULPI bus.
0b — Do not reset
1b — Reset
Operation Mode: Selects the required bit-encoding style during transmit.
00b — Normal operation
01b — Non-driving
10b — Disable bit-stuffing and NRZI encoding
11b — Do not automatically add SYNC and EOP when transmitting; must be used only for
high-speed packets
Termination Select: Controls the internal 1.5 k full-speed pull-up resistor and 45
terminations. Control over bus resistors changes, depending on XCVRSELECT[1:0],
OPMODE[1:0], DP_PULLDOWN and DM_PULLDOWN, as shown in
Transceiver Select: Selects the required transceiver speed.
00b — Enable the high-speed transceiver
01b — Enable the full-speed transceiver
10b — Enable the low-speed transceiver
11b — Enable the full-speed transceiver for low-speed packets (full-speed preamble is
automatically prefixed)
IND_PASS
R/W/S/C
THRU
6
0
R/W/S/C
COMPL
IND_
5
0
Table 22
Rev. 01 — 28 July 2008
reserved
R/W/S/C
provides the bit allocation of the register.
4
0
SUSPENDM
CLOCK_
R/W/S/C
3
0
CARKIT_
R/W/S/C
MODE
2
0
ULPI HS USB transceiver
Table
R/W/S/C
SERIAL
FSLS_
3PIN_
ISP1704A
14.
1
0
© NXP B.V. 2008. All rights reserved.
high-speed
R/W/S/C
SERIAL
FSLS_
6PIN_
0
0
31 of 66