sja1000t-n1 NXP Semiconductors, sja1000t-n1 Datasheet - Page 51
sja1000t-n1
Manufacturer Part Number
sja1000t-n1
Description
Stand-alone Can Controller
Manufacturer
NXP Semiconductors
Datasheet
1.SJA1000T-N1.pdf
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Philips Semiconductors
6.5.2.2
TSEG1 and TSEG2 determine the number of clock cycles per bit period and the location of the sample point, where:
t
t
t
6.5.3
The output control register allows the set-up of different
output driver configurations under software control.
Table 46 Bit interpretation of the output control register (OCR); CAN address 8
2000 Jan 04
SYNCSEG
TSEG1
TSEG2
handbook, full pagewidth
Stand-alone CAN controller
Possible values are BRP = 000001, TSEG1 = 0101 and TSEG2 = 010.
OCTP1
BIT 7
= t
= t
O
scl
scl
= 1
XTAL
UTPUT
Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2)
CAN
(8
(4
t
scl
C
TSEG1.3 + 4
TSEG2.2 + 2
OCTN1
ONTROL
BIT 6
SYNC
SEG
t SYNCSEG
t scl
R
EGISTER
OCPOL1
t CLK
TSEG1.2 + 2
TSEG2.1 + TSEG2.0 + 1)
BIT 5
t TSEG1
TSEG1
nominal bit time
(OCR)
Fig.13 General structure of a bit period.
sample point(s)
Baud Rate Prescaler (BRP)
OCTP0
BIT 4
TSEG1.1 + TSEG1.0 + 1)
t TSEG2
TSEG2
51
This register may be accessed (read/write) if the reset
mode is active. In operating mode, this register is read
only, if the PeliCAN mode is selected. In BasicCAN mode
a ‘FFH’ is reflected.
OCTN0
BIT 3
SYNC
SEG
OCPOL0
BIT 2
TSEG1
OCMODE1
BIT 1
Product specification
SJA1000
MGK628
OCMODE0
BIT 0
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