sja1000t-n1 NXP Semiconductors, sja1000t-n1 Datasheet - Page 9

• Manufacturer Part Number: sja1000t-n1
• Description: Stand-alone Can Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 1 BasicCAN address allocation; note 1
Notes
1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bits of the
2. Test register is used for production testing only. Using this register during normal operation may result in undesired
3. Some bits are writeable in reset mode only (CAN mode and CBP).
2000 Jan 04
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ADDRESS
Stand-alone CAN controller
8-bit CPU address are not decoded: CAN address 32 continues with CAN address 0 and so on).
behaviour of the device.
CAN
control
transmit
buffer
receive
buffer
SEGMENT
control
(FFH)
status
interrupt
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
test
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
(FFH)
clock divider
READ
OPERATING MODE
control
command
test; note 2
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
clock divider; note 3
WRITE
9
control
(FFH)
status
interrupt
acceptance code
acceptance mask
bus timing 0
bus timing 1
output control
test
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
(FFH)
clock divider
READ
RESET MODE
control
command
acceptance code
acceptance mask
bus timing 0
bus timing 1
output control
test; note 2
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
clock divider
Product specification
SJA1000
WRITE