lan83c185 Standard Microsystems Corp., lan83c185 Datasheet - Page 18

• Manufacturer Part Number: lan83c185
• Description: Lan83c185 High Performance Single Chip Low Power 10/100 Physical Layer Transceiver Phy
• Manufacturer: Standard Microsystems Corp.

Revision 0.8 (06-12-08)
4.2.3
4.2.4
4.2.5
4.2.6
GROUP
CODE
00010
00101
01000
10000
00011
01100
Scrambling
Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large
narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power
more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC
regulations to prevent excessive EMI from being radiated by the physical wiring.
The seed for the scrambler is generated from the PHY address, PHYAD[4:0], ensuring that in multiple-
PHY applications, such as repeaters or switches, each PHY will have its own scrambler sequence.
The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data.
NRZI and MLT3 Encoding
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a
serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a
change in the logic level represents a code bit “1” and the logic output remaining at the same level
represents a code bit “0”.
100M Transmit Driver
The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal,
on outputs TXP and TXN, to the twisted pair media via a 1:1 ratio isolation transformer. The 10Base-
T and 100Base-TX signals pass through the same transformer so that common “magnetics” can be
used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination
and impedance matching require external components.
100M Phase Lock Loop (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz
logic and the 100Base-Tx Transmitter.
SYM
V
V
V
V
V
V
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
INVALID, RX_ER if during RX_DV
Table 4.1 4B/5B Code Table (continued)
INTERPRETATION
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
RECEIVER
DATASHEET
18
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
INTERPRETATION
TRANSMITTER
SMSC LAN83C185
Datasheet