lan83c185 Standard Microsystems Corp., lan83c185 Datasheet - Page 40

• Manufacturer Part Number: lan83c185
• Description: Lan83c185 High Performance Single Chip Low Power 10/100 Physical Layer Transceiver Phy
• Manufacturer: Standard Microsystems Corp.

Revision 0.8 (06-12-08)
28.15:0
29.15:8
29.7
23.15:0
ADDRESS
27.15:13
27.12
27:11
27:10
27.9
27.8
27.7
27.6
27.5
27.4
27.3:0
ADDRESS
ADDRESS
ADDRESS
Reserved
SWRST_FAST
SQEOFF
VCOOFF_LP
Reserved
Reserved
Reserved
Reserved
Reserved
XPOL
AUTONEGS
Reserved
Reserved
INT7
WRITE_DATA
NAME
NAME
NAME
NAME
Table 5.49 Register 28 - Special Internal Testability Controls
Table 5.48 Register 27 - Special Control/Status Indications
Table 5.50 Register 29 - Interrupt Source Flags
1 = Accelerates SW reset counter from 256 ms to 10
Disable the SQE test (Heartbeat):
0 - SQE test is enabled.
1 - SQE test is disabled.
Forces the Receive PLL 10M to lock on the reference
clock at all times:
0 - Receive PLL 10M can lock on reference or line as
1 - Receive PLL 10M is locked on the reference clock.
In this mode 10M data packets cannot be received.
Write as 0. Ignore on read.
Write as 0. Ignore on read.
Write as 0. Ignore on read
Write as 0. Ignore on read.
Write as 0. Ignore on read.
Polarity state of the 10Base-T:
0 - Normal polarity
1 - Reversed polarity
Auto-negotiation “ARB” State-machine state
Do not write to this register. Ignore on read.
This field contains the data that will be written to a
specific register on the “Programming” transaction.
Ignore on read.
1 = ENERGYON generated
0 = not source of interrupt
Table 5.47 Register 23 - TSTWRITE
needed (normal operation)
us for production testing.
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
DATASHEET
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
40
RW
RW
RW
RW,
NASR
RW,
NASR
RW
RW
RW
RW
RW
RO
RO
MODE
RW
RO/
LH
RO/
LH
MODE
MODE
MODE
SMSC LAN83C185
DEFAULT
0
DEFAULT
0
0
0
0
0
0
0
0
0
1011
DEFAULT
N/A
DEFAULT
0
0
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