lan83c185 Standard Microsystems Corp., lan83c185 Datasheet - Page 46

• Manufacturer Part Number: lan83c185
• Description: Lan83c185 High Performance Single Chip Low Power 10/100 Physical Layer Transceiver Phy
• Manufacturer: Standard Microsystems Corp.

Revision 0.8 (06-12-08)
5.4.9.2
5.5
5.5.1
5.5.1.1
5.5.1.1.1
MODE[2:0]
000
001
010
100
101
011
110
111
Analog
Mode Bus – MODE[2:0]
The MODE[2:0] bus controls the configuration of the 10/100 digital block.
The analog blocks of the chip are described in this section.
ADC
The ADC is a 6 bit 125 MHz sample rate Analog to Digital Converter designed to serve as the analog
front end of a digital 100Base-Tx receiver.
Functional Description
The ADC has a full flash architecture for maximum speed and minimum latency. An internally
generated 125MHz clock is used to time the sampling and processing.
The ADC has a variable gain, which is controlled by the DSP block. This allows accurate A/D
conversion over the entire range of input signal amplitudes, which is particularly important for lower
amplitude signals (longer cables).
INPUT COMMON MODE
The differential input is applied to the RXP/N signals. For proper operation of the ADC the input
common mode should match the internal differential reference common mode. To achieve this, the
ADC generates the appropriate voltage and drives it via the VCOM signal.
10Base-T Half Duplex. Auto-negotiation disabled.
10Base-T Full Duplex. Auto-negotiation disabled.
100Base-TX Half Duplex. Auto-negotiation
disabled.
CRS is active during Transmit & Receive.
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
100ase-TX Half Duplex is advertised. Auto-
negotiation enabled.
CRS is active during Transmit & Receive.
Repeater mode. Auto-negotiation enabled.
100Base-TX Half Duplex is advertised.
CRS is active during Receive.
Power Down mode. In this mode the PHY wake-up
in Power-Down mode.
All capable. Auto-negotiation enabled.
MODE DEFINITIONS
Table 5.53 MODE[2:0] Bus
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
DATASHEET
46
DEFAULT REGISTER BIT VALUES
REGISTER 0
[13,12,10,8]
X10X
0000
0001
1000
1001
1100
1100
N/A
REGISTER 4
SMSC LAN83C185
[8,7,6,5]
0100
0100
1111
N/A
N/A
N/A
N/A
N/A
Datasheet