lan91c100fd Standard Microsystems Corp., lan91c100fd Datasheet - Page 45

• Manufacturer Part Number: lan91c100fd
• Description: Lan91c100fd Rev. B Feast Fast Ethernet Controller With Full Duplex Capability
• Manufacturer: Standard Microsystems Corp.

2)
Note: The pointer register is shared by any process accessing the LAN91C100FD memory. In order to allow
processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it,
saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1)
2)
3)
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also
required from interrupt service routines.
SMSC DS – LAN91C100FD REV. B
One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY
INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and
therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that when
AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Transmit loading (sometimes interrupt driven)
Receive unloading (interrupt driven)
Transmit Status reading (interrupt driven).
OPTIONS
TWO
STATUS REGISTER
INTERRUPT
FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU
TX EMPTY
ALLOC
RCV
INT
INT
INT
INT
TX
PACKET NUMBER
'NOT EMPTY'
M.S. BIT ONLY
TX DONE
'EMPTY'
CPU ADDRESS
PACKET NUMBER
REGISTER
PACK # OUT
Page 45
'NOT EMPTY'
CSMA ADDRESS
PACKET NUMBER
RX PACKET
NUMBER
RX FIFO
Rev. 03-28-07