lan9215i Standard Microsystems Corp., lan9215i Datasheet - Page 122

• Manufacturer Part Number: lan9215i
• Description: Lan9215i 16-bit Non-pci 10/100 Ethernet Controller With Hp Auto-mdix And Industrial Temperature Support
• Manufacturer: Standard Microsystems Corp.

Revision 2.3 (08-06-08)
6.2
SYMBOL
t
t
cycle
t
t
t
t
t
csdv
t
t
asu
don
doff
doh
csh
nCS, nRD
csl
ah
A[7:1]
Data Bus
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
Note: The “Data Bus” width is 16 bits
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time (see Note below)
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycles.
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Parameters t
csh
and t
Figure 6.1 PIO Read Cycle Timing
csl
Table 6.3 PIO Read Timing
must be extended using wait states to meet the t
DATASHEET
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX and Industrial Temperature Support
122
MIN
165
32
13
0
0
0
0
TYP
133
cycle
MAX
30
7
minimum.
SMSC LAN9215i
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns