lan9221 Standard Microsystems Corp., lan9221 Datasheet - Page 132

• Manufacturer Part Number: lan9221
• Description: High-performance 16-bit Non-pci 10/100 Ethernet Controller With Variable Voltage I/o
• Manufacturer: Standard Microsystems Corp.

Revision 2.6 (12-04-08)
6.4
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note 6.3
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
When VDDVARIO is 3.3V or 2.5V, the maximum T
1.8V, the maximum T
Figure 6.3 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
doff
DATASHEET
time is 9ns.
132
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
MIN
13
45
0
0
0
0
doff
time is 7ns. When VDDVARIO is
TYP
SMSC LAN9221/LAN9221i
Note 6.3
MAX
30
40
Datasheet
UNITS
ns
ns
ns
ns
ns
ns
ns