lan9221 Standard Microsystems Corp., lan9221 Datasheet - Page 133

• Manufacturer Part Number: lan9221
• Description: High-performance 16-bit Non-pci 10/100 Ethernet Controller With Variable Voltage I/o
• Manufacturer: Standard Microsystems Corp.

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
6.5
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
In this mode the upper address inputs are not decoded, and any read of the LAN9221/LAN9221i will
read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access.
This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This
mode is useful when the host processor must increment its address when accessing the
LAN9221/LAN9221i. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing
characteristics as the address lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits.
Note 6.4
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
RX Data FIFO Direct PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order.
When VDDVARIO is 3.3V or 2.5V, the maximum T
1.8V, the maximum T
Figure 6.4 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
doff
DATASHEET
time is 9ns.
133
MIN
45
32
13
0
0
0
0
doff
time is 7ns. When VDDVARIO is
TYP
Note 6.4
MAX
Revision 2.6 (12-04-08)
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns