fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 67
![no-image](/images/no-image-200.jpg)
fdc37m707
Manufacturer Part Number
fdc37m707
Description
Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
Manufacturer
Standard Microsystems Corp.
Datasheet
1.FDC37M707.pdf
(194 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 67 of 194
- Download datasheet (678Kb)
The following section describes the operation of
the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data
byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is
double buffered; this uses an additional shift
register to receive the serial data stream and
convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The
shift register is not accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be
transmitted.
buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a
serial format. This shift register is loaded from
the Transmit Buffer when the transmission of
the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the
enables of the five interrupt sources of the Serial
Port interrupt. It is possible to totally disable the
interrupt system by resetting bits 0 through 3 of
this register. Similarly, setting the appropriate
bits of this register to a high, selected interrupts
can be enabled. Disabling the interrupt system
inhibits the Interrupt Identification Register and
disables any Serial Port interrupt out of the
FDC37M70x. All other system functions operate
in their normal manner, including the Line
Status and MODEM Status Registers.
contents of the Interrupt Enable Register are
described below.
The transmit buffer is double
The
67
Bit 0
This bit enables the Received Data Available
Interrupt (and timeout interrupts in the FIFO
mode) when set to logic "1".
Bit 1
This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic "1".
Bit 2
This bit enables the Received Line Status
Interrupt when set to logic "1".
sources causing the interrupt are Overrun,
Parity, Framing and Break.
Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt
when set to logic "1". This is caused when one
of the Modem Status Register bits changes
state.
Bits 4 through 7
These bits are always logic "0".
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location
as the IIR. This register is used to enable and
clear the FIFOs, set the RCVR FIFO trigger
level. Note: DMA is not supported. The UART1
and UART2 FCR’s are shadowed in the UART1
FIFO Control Shadow Register (LD8:CRC3[7:0])
and UART2 FIFO Control Shadow Register
(LD8:CRC4[7:0]).
Bit 0
Setting this bit to a logic "1" enables both the
XMIT and RCVR FIFOs.
logic "0" disables both the XMIT and RCVR
FIFOs and clears all bytes from both FIFOs.
When changing from FIFO Mode to non-FIFO
(16450) mode, data is automatically cleared
from the FIFOs.
other bits in this register are written to or they
will not be properly programmed.
This bit must be a 1 when
Clearing this bit to a
The Line Status
The error
Related parts for fdc37m707
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![USB2503-HZH](/images/no-image3.png)
Part Number:
Description:
Interface, Integrated USB2.0 Compatible 3-Port Hub
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![lan91c100fd](/images/no-image3.png)
Part Number:
Description:
Lan91c100fd Rev. B Feast Fast Ethernet Controller With Full Duplex Capability
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![lan91c100](/images/no-image3.png)
Part Number:
Description:
Feast ? Ast Ethernet Controller
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![com20022i](/images/no-image3.png)
Part Number:
Description:
Com20022i 10 Mbps Arcnet Ansi 878.1 Controller With 2k X 8 On-chip Ram
Manufacturer:
Standard Microsystems Corp.
![lpc47n207-jv](/images/no-image3.png)
Part Number:
Description:
Lpc47n207 Lpc Super I/o Irda Hot Docking Chip With Uart Data Brief
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![lpc47s457-ns](/images/no-image3.png)
Part Number:
Description:
Advanced I/o With X-bus Interface
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![com81c17](/images/no-image3.png)
Part Number:
Description:
Twenty Pin Uart Tpuart Corporation
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![MSD7262](/images/no-image3.png)
Part Number:
Description:
Enhanced Small Device Interface Controller
Manufacturer:
Standard Microsystems Corp.
![EMC2301](/images/no-image3.png)
Part Number:
Description:
Rpm-based Pwm Fan Controller
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC2302](/images/no-image3.png)
Part Number:
Description:
Rpm-based Pwm Fan Controller
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC1001](/images/no-image3.png)
Part Number:
Description:
Emc1001 1.5?c Smbus Temperature Sensor In Miniature Sot-23
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC1043](/images/no-image3.png)
Part Number:
Description:
1 Degree C Triple Temperature Sensor With Beta Compensation And Hotter Of Two Zones
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC1046](/images/no-image3.png)
Part Number:
Description:
1 Degree C Multiple Temperature Sensor With Beta Compensation And Hottest Of Thermal Zones
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC1053](/images/no-image3.png)
Part Number:
Description:
1 Degree C Triple Temperature Sensor With Resistance Error Correction & Hotter Of Two Zones
Manufacturer:
Standard Microsystems Corp.
Datasheet:
![EMC1063](/images/no-image3.png)
Part Number:
Description:
1 Degree C Triple Temperature Sensor With Hotter Of Two Zones
Manufacturer:
Standard Microsystems Corp.
Datasheet: