fdc37m707 Standard Microsystems Corp., fdc37m707 Datasheet - Page 86

• Manufacturer Part Number: fdc37m707
• Description: Fdc37m707 Enhanced Super I/o Controller With Wake-up Features
• Manufacturer: Standard Microsystems Corp.

EPP 1.9 Read
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1
2.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
If the EPP bus is not ready (nWAIT is active
low) when nDATASTB goes active then the
read can complete when nWAIT goes
inactive high.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
WRITE or before nDATASTB goes active.
The read can complete once nWAIT is
determined inactive.
The host selects an EPP register and drives
nIOR active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
The chip tri-states the PData bus and
deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT, indicating that
PData is valid and the chip may begin the
termination phase of the cycle.
a)
b)
The chip latches the data from the
PData bus for the SData bus and
deasserts nDATASTB or nADDRSTRB.
This marks the beginning of the
termination phase.
The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY
complete the read cycle.
allowing
the
host
to
86
9.
10. Chip
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the cycle
nIOR or nIOW deasserted).
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
Data or Address cycle.
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
time.
nWAIT is inactive high.
Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
nPDATA in preparation for the next cycle.
The write cycle can complete when
may modify nWRITE, PDIR
IOCHRDY is driven
If a time-out
and