uja1076tw/5v0/wd NXP Semiconductors, uja1076tw/5v0/wd Datasheet - Page 7

• Manufacturer Part Number: uja1076tw/5v0/wd
• Description: High-speed Can Core System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1076_1
Product data sheet
6.1.1 Introduction
6.1.2 Off mode
6.1.3 Standby mode
6.1
The system controller manages register configuration and controls the internal functions
of the SBC. Detailed device status information is collected and presented to the
microcontroller. The system controller also provides the reset and interrupt signals.
The system controller is a state machine. The SBC operating modes, and how transitions
between modes are triggered, are illustrated in
more detail in the following sections.
The SBC switches to Off mode from all other modes if the battery supply drops below the
power-off detection threshold (V
and the bus systems are in a high-resistive state. The CAN bus pins are floating in this
mode.
As soon as the battery supply rises above the power-on detection threshold (V
the SBC goes to Standby mode, and a system reset is executed (reset pulse width of
t
The SBC will enter Standby mode:
In Standby mode, V1 is switched on. The CAN transceiver will either be in a low-power
state (Lowpower mode; STBCC = 1; see
completely switched off (Off mode; STBCC = 0) - see
running in Timeout mode or Off mode, depending on the state of the WDOFF pin and the
setting of the watchdog mode control bit (WMC) in the WD_and_Status register
The SBC will exit Standby mode if:
w(rst)
System Controller
•
•
•
•
•
•
•
From Off mode if V
From Sleep mode on the occurrence of a CAN or local wake-up event
From Overtemp mode if the chip temperature drops below the overtemperature
protection release threshold, T
From Normal mode if bit MC is set to 00 or a system reset is performed (see
Section
Normal mode is selected by setting bits MC to 10 (V2 disabled) or 11 (V2 enabled)
Sleep mode is selected by setting bits MC to 01
The chip temperature rises above the OTP activation threshold, T
SBC to enter Overtemp mode
, long or short; see
6.5)
Rev. 01 — 1 December 2009
BAT
Section 6.5.1
rises above the power-on detection threshold (V
th(det)poff
th(rel)otp
and
). In Off mode, the voltage regulators are disabled
Table
Table
High-speed CAN core system basis chip
Figure
6) with bus wake-up detection enabled or
10).
Section
3. These modes are discussed in
6.7.1. The watchdog can be
th(act)otp
UJA1076
© NXP B.V. 2009. All rights reserved.
th(det)pon
, causing the
th(det)pon
(Table
)
7 of 45
),
4).