uja1076tw/5v0/wd NXP Semiconductors, uja1076tw/5v0/wd Datasheet - Page 8
uja1076tw/5v0/wd
Manufacturer Part Number
uja1076tw/5v0/wd
Description
High-speed Can Core System Basis Chip
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1076TW5V0WD.pdf
(45 pages)
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NXP Semiconductors
UJA1076_1
Product data sheet
Fig 3.
power-on threshold V
power-off threshold V
UJA1076 system controller
(from all modes)
V
BAT
V
successful
watchdog
BAT
trigger
below
below
th(det)pon
th(det)poff
CAN: Active/Lowpower
watchdog: Window/
high resistance
watchdog: OFF
V2: ON/OFF
CAN: Off and
Timeout/Off
INTN: HIGH
MC = 1x
Normal
V1: OFF
V2: OFF
V1: ON
reset event or
Off
MC = 00
watchdog overflow or
Rev. 01 — 1 December 2009
V1 undervoltage
power-on threshold V
limp home = LOW (active)
MC = 10 or MC = 11
watchdog: OFF
high resistance
V
one wake-up enabled and
CAN: Off and
Overtemp
BAT
V1: OFF
V2: OFF
no wake-up pending
INTN = HIGH and
watchdog: Timeout/Off
above
MC = 01 and
CAN: Lowpower/Off
Standby
th(det)pon
MC = 00
V2: OFF
V1: ON
OTP release threshold T
wake-up event if enabled
High-speed CAN core system basis chip
chip temperature below
OTP activatrion threshold T
watchdog
trigger
chip temperature above
th(rel)otp
one wake-up enabled and
from Standby or Normal
CAN: Lowpower/Off
no wake-up pending
INTN = HIGH and
watchdog: OFF
RSTN: LOW
MC = 01 and
UJA1076
V1: OFF
V2: OFF
MC = 01
© NXP B.V. 2009. All rights reserved.
Sleep
th(act)otp
015aaa110
8 of 45
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