dp8421a National Semiconductor Corporation, dp8421a Datasheet - Page 16

• Manufacturer Part Number: dp8421a
• Description: Microcmos Programmable 256k/1m/4m Dynamic Ram Controller/drivers
• Manufacturer: National Semiconductor Corporation

4 0 Port A Access Modes
4 4 READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE
There are 2 methods by which this chip can be used to do
read-modify-write access cycles The first method involves
doing a late write access where the WIN input is asserted
some delay after CAS is asserted The second method in-
volves doing a page mode read access followed by a page
mode write access with RAS held low (see Figure 9c )
CASn must be toggled using the ECASn inputs and WIN has
to be changed from negated to asserted (read to write)
while CAS is negated This method is better than changing
There may be idle states inserted here by the CPU
FIGURE 9c Read-Modify-Write Access Cycle
(Continued)
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WIN from negated to asserted in a late write access be-
cause here a problem may arise with DATA IN and DATA
OUT being valid at the same time This may result in a data
line trying to drive two different levels simultaneously The
page mode method of a read-modify-write access allows
the user to have transceivers in the system because the
data in (read data) is guaranteed to be high impedance dur-
ing the time the data out (write data) is valid
TL F 8588 – G2