m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 50

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)
(3) BCLR (Buffer Clear) Bit (b12)
This bit indicates valid value when the E0req bit of this register is set to “0”.
This bit clears the data written to the CPU side buffer.
This bit automatically returns to “0” after the buffer is cleared.
2 0 0 4 . 1 1 . 0 1
Note:
Note:
Note:
When set to control write transfer (ISEL bit = “0”)
When set to control read transfer (ISEL bit = “1”)
When set to control write transfer (ISEL bit = “0”)
When set to control read transfer (ISEL bit = “1”)
When this bit is set to “1”, the buffer is at CPU side and can be read.
This bit is set to “1” at completion of receiving data.
The conditions of receive completion depend on the CTRW bit.
When this bit is set to “1”, the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).
This bit is cleared to “0” due to one of the reasons as follows:
When this bit is set to “0”, the buffer is at CPU side and can be written.
This bit is cleared to “0” due to one of the reasons as follows:
The transmit completion is changed by the CTRR bit.
When this bit is set to “0” if the EPB_EMPE bit is set to “1”, the EPB_EMP_OVR bit is set to “1” (buffer
empty/size over error interrupt occurs).
This bit is set to “1” due to one of the reasons as follows:
The write completion also is changed by the CTRR bit.
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:
Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to the
IVAL bit. For details, refer to “IVAL bit”.
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
When the IVAL bit is set to “1”, make sure to set the EP0_PID bits to “00” before executing the aforesaid
operations.
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p a g e 5 0 o f 1 2 2
Reads out all the data received in the CPU side buffer.
Writes “1” to the BCLR bit.
Transmits completely SIE side buffer.
Writes “1” to the BCLR bit.
Completely writes the transmit data to CPU side buffer.
Writes “1” to this bit.
When “1” is written to this bit, the write is forcibly completed. When some written data exists
in the buffer, that data is transmitted as the short packet. Here, if the buffer is empty or
cleared, the zero-length packet is transmitted. The buffer can be cleared using the BCLR bit.
Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit
and to the BCLR bit. In this case the buffer is cleared by setting “1” to BCLR bit, and this bit
is cleared to “0” after the zero-length packet is transmitted.
Clears CPU side buffer.
Clears the IVAL bit of this register.
Clears the ODLN bits of this register.
Clears CPU side buffer.
Clears SIE side buffer (Unlike the other endpoints, the SIE side buffer can also be cleared by
this bit).
Clears the IVAL bit of this register.