m66291 Renesas Electronics Corporation., m66291 Datasheet - Page 79

• Manufacturer Part Number: m66291
• Description: Assp Usb2.0 Device Controller
• Manufacturer: Renesas Electronics Corporation.

M 6 6 2 9 1 G P / H P
2.40 Epi Configuration Registers 1 (i=1~6)
R e v 1 . 0 1
(1) EPi_PID (Response PID) Bits (b15~b14)
(2) EPi_NULMD (Zero-Length Packet Addtion Transmit Mode) Bit (b12)
15~14
b15
EP1 Configuration Register 1 (EP1_1CONFIG)
EP2 Configuration Register 1 (EP2_1CONFIG)
EP3 Configuration Register 1 (EP3_1CONFIG)
EP4 Configuration Register 1 (EP4_1CONFIG)
EP5 Configuration Register 1 (EP5_1CONFIG)
EP6 Configuration Register 1 (EP6_1CONFIG)
9~0
13
12
11
10
0
-
-
b
EPi_PID
These bits set the PID to be responded to the host.
These bits are valid only when the transfer type is set to bulk transfer mode or interrupt transfer mode
(EPi_TYP bits = “01” or “10”). Set these bits to “01” at isochronous transfer mode (EPi_TYP bits = “11”).
When these bits are set to “00”, the NAK response is executed, regardless of the buffer state.
When these bits are set to “01”;
<When set to OUT buffer (EPi_DIR bit = “0”)>
<When set to IN buffer (EPi_DIR bit = “1”)>
When these bits are set to “1x”, the STALL response is executed, regardless of the buffer state.
When set to OUT buffer, if a data exceeding the maximum packet size is received, regardless of these bit
values, these bits are set automatically to “1x” (STALL).
2 0 0 4 . 1 1 . 0 1
EPi_PID
Response PID
Reserved. Set it to “0”.
EPi_NULMD
Zero-Length Packet Addtion Transmit Mode
EPi_ACLR
OUT Buffer Automatic Clear Mode
EPi_Octl
Register 8-Bit Mode
EPi_MXPS
Maximum Packet Size
14
0
-
-
•
•
•
•
ACK response after receiving the data with the SIE side buffer in the receive ready state.
NAK response with the SIE side buffer in the receive not ready state.
Transmits the data with the SIE side buffer in transmit ready state.
NAK response with the SIE side buffer not in the transmit ready state.
13
0
-
-
When the SIE side buffer is not in receive ready state, if the OUT token is received, the
EPB_NRD bit is set to “1”.
When the SIE side buffer is in the transmit not ready state, if the IN token is received, the
EPB_NRD bit is set to “1”.
p a g e 7 9 o f 1 2 2
NULMD
EPi_
12
0
-
-
Bit name
ACLR
EPi_
11
0
-
-
EPi_
Octl
10
0
-
-
9
0
-
-
00 : NAK
01 : BUF
1x : STALL
0 :
1 :
0 :
1 :
0 :
1 :
Upper size limit of the data transmitted/received in one packet
8
0
-
-
(Transmits response PID/data according to the state of
buffer etc,)
Disable to transmit zero-length packet automatically
Enable to transmit zero-length packet automatically
Exit buffer clear mode
Buffer clear mode
Make sure to set “0” after setting “1”.
CPU/Dn_FIFO Data Register is 16-bit mode
CPU/Dn_FIFO Data Register is 8-bit mode
Interrupt transfer
Bulk transfer
Isochronous transfer
7
0
-
-
6
1
-
-
Function
EPi_MXPS
5
0
-
-
:0~64
:only 8,16,32 and 64
:0~1023
4
0
-
-
3
0
-
-
2
0
-
-
<H/W reset : H'0040>
<Address : H’6A>
<Address : H’6E>
<Address : H’62>
<Address : H’66>
<Address : H’72>
<Address : H’76>
<USB bus reset : ->
<S/W reset : ->
1
0
-
-
R
0
b0
0
-
-
W
0