lmh6522sqe National Semiconductor Corporation, lmh6522sqe Datasheet - Page 21

• Manufacturer Part Number: lmh6522sqe
• Description: High Performance Quad Dvga
• Manufacturer: National Semiconductor Corporation

DIGITAL CONTROL
The LMH6522 will support two modes of control, parallel
mode and serial mode (SPI compatible). Parallel mode is
fastest and requires the most board space for logic line rout-
ing. Serial mode is compatible with existing SPI compatible
systems.
The LMH6522 has gain settings covering a range of 31 dB.
To avoid undesirable signal transients the LMH6522 should
not be powered on with large inputs signals present. Careful
planning of system power on sequencing is especially impor-
tant to avoid damage to ADC inputs.
The LMH6522 was designed to interface with 2.5V to 5V
CMOS logic circuits. If operation with 5V logic is required care
should be taken to avoid signal transients exceeding the DV-
GA supply voltage. Long, unterminated digital signal traces
are particularly susceptible to these transients. Signal volt-
ages on the logic pins that exceed the device power supply
voltage may trigger ESD protection circuits and cause unre-
liable operation.
Some pins on the LMH6522 have different functions depend-
ing on the digital control mode. These functions will be de-
scribed in the sections to follow.
Pins with Dual Functions
Pin 45 requires external bias. See Serial Mode Section for Details.
PARALLEL INTERFACE
Parallel mode offers the fastest gain update capability with the
drawback of requiring the most board space dedicated to
control lines. When designing a system that requires very fast
gain changes parallel mode is the best selection. To place the
LMH6522 into parallel mode the MODE pin (pin 5) is set to
the logical zero state. Alternately the MODE pin can be con-
nected directly to ground.
The attenuator control pins are internally biased to logic high
state with weak pull up resistors. The MODE pin has a weak
internal resistor to ground. The enable pins bias to a mid logic
state which is the Low Power Mode.
The LMH6522 has a 5-bit gain control bus. Data from the gain
control pins is immediately sent to the gain circuit (i.e. gain is
changed immediately). To minimize gain change glitches all
gain pins should change at the same time. In order to achieve
the very fast gain step switching time the internal gain change
circuit is very fast. Gain glitches could result from timing skew
between the gain set bits. This is especially the case when a
small gain change requires a change in state of three or more
gain control pins. If necessary the DVGA could be put into a
disabled state while the gain pins are reconfigured and then
brought active when they have settled.
ENA and ENB pins are provided to reduce power consump-
tion by disabling the highest power portions of the LMH6522.
The gain register will preserve the last active gain setting dur-
ing the disabled state. These pins will float high and can be
left disconnected if they won't be used. If the pins are left dis-
connected a 0.01uF capacitor to ground will help prevent
external noise from coupling into these pins. See the Typical
Performance section for disable and enable timing informa-
tion.
Pin
45
46
47
48
MODE = 0
A4
A3
A2
A1
MODE = 1
SDO*
SDI
CSb
CLK
21
SPI COMPATIBLE SERIAL INTERFACE
Serial interface allows a great deal of flexibility in gain pro-
gramming and reduced board complexity. Using only 4 wires
for both channels allows for significant board space savings.
The trade off for this reduced board complexity is slower re-
sponse time in gain state changes. For systems where gain
is changed only infrequently or where only slow gain changes
are required serial mode is the best choice. To place the
LMH6522 into serial mode the MODE pin (Pin 5) should be
put into the logic high state. Alternatively the MODE pin an be
connected directly to the 5V supply bus.
The LMH6522 has a serial interface that allows access to the
control registers. The serial interface is a generic 4-wire syn-
chronous interface that is compatible with SPI type interfaces
that are used on many microcontrollers and DSP controllers.
The serial mode is active when the two mode pins are set as
follows: MODE=1. In this configuration the pins function as
shown in the pin description table. The SPI interface uses the
following signals: clock input (CLK), serial data in (SDI), serial
data out, and serial chip select (CS). The chip select pin is
active low.
The enable pins are inactive in the serial mode. These pins
can be left disconnected for serial mode.
The CLK pin is the serial clock pin. It is used to register the
input data that is presented on the SDI pin on the rising edge;
and to source the output data on the SDO pin on the falling
edge. User may disable clock and hold it in the low state, as
long as the clock pulse-width minimum specification is not vi-
olated when the clock is enabled or disabled.
The CSb pin is the chip select pin. The b indicates that this
pin is actually a “NOT chip select” since the chip is selected
in the logic low state. Each assertion starts a new register
access - i.e., the SDATA field protocol is required. The user
is required to deassert this signal after the 16th clock. If the
CSb pin is deasserted before the 16th clock, no address or
data write will occur. The rising edge captures the address
just shifted-in and, in the case of a write operation, writes the
addressed register. There is a minimum pulse-width require-
ment for the deasserted pulse - which is specified in the
Electrical Specifications section.
The SDI pin is the input pin for the serial data. It must observe
setup / hold requirements with respect to the SCLK. Each cy-
cle is 16-bits long
The SDO pin is the data output pin. This output is normally at
a high impedance state, and is driven only when CSb is as-
serted. Upon CSb assertion, contents of the register ad-
dressed during the first byte are shifted out with the second 8
SCLK falling edges. Upon power-up, the default register ad-
dress is 00h. The SDO pin requires external bias for clock
FIGURE 10. Parallel Mode Connection
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