lmh6522sqe National Semiconductor Corporation, lmh6522sqe Datasheet - Page 5

• Manufacturer Part Number: lmh6522sqe
• Description: High Performance Quad Dvga
• Manufacturer: National Semiconductor Corporation

Power Requirements
ICC
P
I
ICC
All Digital Inputs Except Enables
VIL
VIH
IIH
IIL
Enable Pins
VIL
VIM
VIH
VSB
IIL
IIM
IIH
Parallel Mode Timing
t
t
Serial Mode
f
Low Power Mode
(Enable pins are self biased)
I
I
I
OIP3
P1dB
HD2
HD2
HD3
HD3
BIAS
GS
GH
CLK
CC
BIAS
CC
Symbol
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Gain Step Error
Gain Step Error
Gain Step Phase Shift
Gain Step Phase Shift
Gain Step Switching Time
Enable/ Disable Time
Supply Current
Power
Output Pin Bias Current
Disabled Supply Current
Logic Compatibility
Logic Input Low Voltage
Logic Input High Voltage
Logic Input High Input Current
Logic Input Low Input Current
Logic Input Low Voltage
Logic Input Mid Level
Logic Input High Level
Enable Pin Self Bias Voltage
Input Bias Current, Logic Low
Input Bias Current, Logic Mid
Input Bias Current, Logic High
Setup Time
Hold Time
SPI Clock Frequency
Total Supply Current
Output Pin Bias Current
Disabled Supply Current
Output Intermodulation Intercept
Point
1dB Compression Point
Second Order Harmonic Distortion f = 100 MHz, V
Second Order Harmonic Distortion f = 200 MHz,V
Third Order Harmonic Distortion
Third Order Harmonic Distortion
Parameter
Any two adjacent steps over entire range
Any two adjacent steps, 0 dB attenuation
to 23 dB attenuation
Any two adjacent steps over entire range
Any two adjacent steps, 0dB attenuation
to 23 dB attenuation
Settled to 90% level
External inductor, no load, V
TTL, 2.5V CMOS, 3.3V CMOS, 5V CMOS
Digital Input Voltage = 2.0V
Digital Input Voltage = 0.4V
Amplifier disabled
Amplifier Low Power Mode
Amplifier High Power Mode
No external load
Digital input voltage = 0.2V
Digital input voltage = 1.5V
Digital input voltage = 3.0V
50% duty cycle, ATE tested @ 20MHz
all four channels in low power mode
External Inductor, No Load, V
200mV
Enable Pin < 0.4V
f = 200 MHz, V
f = 100 MHz, V
f = 200 MHz, V
Conditions
OUT
OUT
OUT
OUT
OUT
5
= 2 V
=2 V
= 2 V
= 2 V
= 4 dBm per tone
PPD
PPD
PPD
PPD
OUT
OUT
< 200 mV
<
(Note
Min
2.0
0.6
2.2
20
0
0
3
3
6)
(Note
−200
±0.5
±0.1
1.37
Typ
−47
−90
−79
−91
−79
200
465
500
370
2.3
±3
±2
−9
20
36
74
28
50
26
74
44
16
5)
(Note
Max
2.43
485
398
0.4
5.0
0.4
1.9
5
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6)
Degrees
Degrees
Units
MHz
dBm
dBm
dBc
dBc
dBc
dBc
mA
mA
mA
mA
mA
mA
dB
dB
μA
μA
µA
µA
µA
ns
us
W
ns
ns
V
V
V
V
V
V