sta015t STMicroelectronics, sta015t Datasheet - Page 17

• Manufacturer Part Number: sta015t
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

REQ_POL
Address: 0x0C (12)
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x00
The REQ_POL registers is used to program the
polarity of the DATA_REQ line.
Default polarity (the source sends data when the
DATA_REQ line is high)
Inverted polarity (the source sends data when the
DATA_REQ line is low)
SCKL_POL
Address: 0x0D (13)
Type: R/W
Software Reset: 0x04
Hardware Reset: 0x04
X = don’t care
SCKL_POL is used to select the working polarity
of the Input Serial Clock (SCKR).
(1) If SCKL_POL is set to 0x00, the data (SDI)
(2) If SCKL_POL is set to 0x04, the data (SDI)
ERROR_CODE
Address: 0x0F (15)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
MSB
MSB
b7
b7
b7
X
0
0
are sent with the falling edge of SCKR
and sampled on the rising edge.
are sent with the rising edge of SCKR and
sampled on the falling edge.
b6
X
b6
b6
0
0
b5
X
b5
b5
0
0
b4
X
b4
b4
0
0
b3
X
b3
b3
0
0
b2
0
1
b2
b2
0
1
b1
0
0
b1
b1
0
0
LSB
b0
0
0
LSB
LSB
b0
b0
1
1
(1)
(2)
X = don’t care
ERROR_CODE register contains the last error
occourred if any. The codes can be as follows:
SOFT_RESET
Address: 0x10 (16)
Type: WO
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care; 0 = normal operation; 1 = reset
When this register is written, a soft reset occours.
The STA015 core command register and the in-
terrupt register are cleared. The decoder goes in
to idle mode.
PLAY
Address: 0x13 (19)
Type: R/W
Software Reset: 0x01
Hardware Reset: 0x01
X = don’t care; 0 = normal operation; 1 = play
The PLAY command is handled according to the
state of the decoder, as described in section 2.5.
PLAY only becomes active when the decoder is
in DECODE mode.
MSB
MSB
MSB
b7
b7
b7
X
X
X
Code
0x2X
0x3X
0x00
0x01
0x02
0x04
0x10
b6
b6
b6
X
X
X
EC5
No error since the last SW or HW Reset
b5
b5
b5
X
X
STA015-STA015B-STA015T
Audio synch word not found
EC4
b4
b4
b4
X
X
MPEG Decoding errors
Ancillary data not read
MPEG Header error
DATA not available
EC3
Description
CRC Failure
b3
b3
b3
X
X
EC2
b2
b2
b2
X
X
EC1
b1
b1
b1
X
X
LSB
EC0
LSB
LSB
17/44
b0
b0
b0
0
1
0
1