sta381bws STMicroelectronics, sta381bws Datasheet - Page 147

• Manufacturer Part Number: sta381bws
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA381BWS
The output PLL frequency formula is:
where Fin is the input clock frequency from the pad.
Table 164. PLL factors
Table 165. PLL register 0x43 bits
Table 166. PLL register 0x44 bits
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PLL parameter
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FRAC
NDIV
IDIV
RST
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL_DITH(1:0)
PLL_IDIV (3:0)
PLL_STBBYP
Fin
PLL_DPD
PLL_FCT
PLL_STB
Doc ID 018937 Rev 2
Name
Name
NDIV
×
⎛
⎝
-------------------------- -
(
Register description: Sound Terminal compatibility
IDIV
(
NDIV
Min
‘00’: PLL clock dithering disabled
‘01’: PLL clock dithering enabled (triangular))
‘10’: PLL clock dithering enabled (rectangular)
‘11’: Reserved
PLL loop divider.
‘0’: any PLL dividers change is implemented via PLL
power-down
‘1’: PLL divider change will happen without PLL
power-down
‘0’: PLL use integer ratio
‘1’: PLL use fractional ratio
PLL synchronous divider changes strobe
‘0’: PLL_STB is active
‘1’: PLL_STB control is bypassed
Input PLL divider
+
0
0
5
1
)
)
+
⎛
⎝
FRAC
---------------- -
65536
⎞
⎠
Description
Description
⎞
⎠
65535
Max
55
3
147/168