sta381bw STMicroelectronics, sta381bw Datasheet - Page 88

• Manufacturer Part Number: sta381bw
• Description: Sound Terminal 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

Register description: New Map
88/168
Table 82.
Table 83.
Table 84.
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4
3
2
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLL register 0x54 bits
PLL register 0x55 bits
PLL register 0x56 bits
RST
RST
RST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL_DITH[1:0]
PLL_STBBYP
PLL_IDIV[3:0] Input PLL divider
BOOST32K
PLL_DIRP
PLL_PWD
PLL_NDIV
PLL_BYP
OSC_PD
PLL_DPD
PLL_FCT
PLL_STB
Name
Name
Name
Doc ID 018835 Rev 2
‘0’: PLL configuration is determined by MCS bits
‘1’: PLL configuration is determined by FRAC, IDIV and NDIV
‘0’: PLL normal behavior
‘1’: PLL is in power-down mode.
‘0’: sys clock is from PLL
‘1’: sys clock is from external pin (PLL is bypassed)
0 - Normal behavior
1 - Internal oscillator is in power-down
‘0’: Input oversampling selected by IR bits
‘1’: Input oversampling is selected x3
0 - any PLL dividers changes is implemented via PLL
power down
1 - PLL divider change will happen without PLL power
down
‘0’: PLL use integer ratio
‘1’: PLL use fractional ratio
PLL synchronous divider changes strobe
‘0’: PLL_STB is active
‘1’: PLL_STB control is bypassed
“00”: PLL clock dithering disabled
“01”: PLL clock dithering enabled (triangular)
“10”: PLL clock dithering enabled (rectangular)
“11”: reserved
PLL loop divider
Description
Description
Description
STA381BW